Patents by Inventor Parag R. Maharana
Parag R. Maharana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11836380Abstract: A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.Type: GrantFiled: June 22, 2021Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake, Samir Mittal
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Publication number: 20230362280Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.Type: ApplicationFiled: July 13, 2023Publication date: November 9, 2023Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand
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Patent number: 11706317Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores the data items at the memory locations separated by different memory regions according to different contexts.Type: GrantFiled: December 28, 2020Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand
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Patent number: 11573901Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.Type: GrantFiled: December 28, 2020Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand, Parag R. Maharana
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Patent number: 11561845Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.Type: GrantFiled: May 14, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
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Publication number: 20220398194Abstract: A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.Type: ApplicationFiled: August 15, 2022Publication date: December 15, 2022Inventors: Anirban Ray, Parag R. Maharana, Gurpreet Anand
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Patent number: 11416395Abstract: A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.Type: GrantFiled: August 3, 2018Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Anirban Ray, Parag R. Maharana, Gurpreet Anand
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Publication number: 20220197820Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory allocation value in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context.Type: ApplicationFiled: March 11, 2022Publication date: June 23, 2022Inventors: Anirban Ray, Parag R. Maharana
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Patent number: 11275696Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory allocation value in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context.Type: GrantFiled: June 5, 2020Date of Patent: March 15, 2022Assignee: Micron Technology, Inc.Inventors: Anirban Ray, Parag R. Maharana
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Publication number: 20210349638Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Mittal
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Publication number: 20210311665Abstract: A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.Type: ApplicationFiled: June 22, 2021Publication date: October 7, 2021Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake, Samir Mittal
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Patent number: 11099789Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.Type: GrantFiled: August 21, 2018Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Mittal
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Patent number: 11068203Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.Type: GrantFiled: March 15, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand, Samir Rajadnya, Paul Stonelake, Samir Mittal
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Publication number: 20210117326Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand, Parag R. Maharana
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Publication number: 20210120099Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.Type: ApplicationFiled: December 28, 2020Publication date: April 22, 2021Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand
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Patent number: 10877892Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.Type: GrantFiled: July 11, 2018Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Anirban Ray, Samir Mittal, Gurpreet Anand, Parag R. Maharana
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Patent number: 10880401Abstract: A memory system having one or more memory components and a controller. The controller can receive access requests from a communication connection. The access requests can identify data items associated with the access requests, addresses of the data items, and contexts of the data items in which the data items are used for the access requests. The controller can identify separate memory regions for separate contexts respectively, determine placements of the data items in the separate memory regions based on the contexts of the data items, and determine a mapping between the addresses of the data items and memory locations that are within the separate memory regions corresponding to the contexts of the data items. The memory system stores store the data items at the memory locations separated by different memory regions according to different contexts.Type: GrantFiled: November 7, 2018Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Parag R. Maharana, Anirban Ray, Gurpreet Anand
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Publication number: 20200301848Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory allocation value in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Inventors: Anirban Ray, Parag R. Maharana
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Publication number: 20200272530Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Samir Mittal, Gurpreet Anand, Anirban Ray, Parag R. Maharana
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Patent number: 10691611Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory ratio in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context. A ratio between the amount of the first memory and an amount of the second memory allocated for the execution of the set of instructions in the context is in accordance with the memory ratio.Type: GrantFiled: July 13, 2018Date of Patent: June 23, 2020Assignee: Micron Technology, Inc.Inventors: Anirban Ray, Parag R. Maharana