Patents by Inventor Parag R. Maharana

Parag R. Maharana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8984234
    Abstract: A method and system for managing a cache for a host machine is disclosed. The method includes: indicating each cache line in the cache as being in a transitional meta-state when any virtual machine hosted on the host machine moves out of the host machine; each time a particular cache line is accessed, indicating that particular cache line as no longer in the transitional meta-state; and marking the cache lines still in the transitional meta-state as invalid when a virtual machine moves back to the host machine.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 17, 2015
    Assignee: LSI Corporation
    Inventors: Parag R. Maharana, Luca Bert, Earl Cohen
  • Patent number: 8954788
    Abstract: In one embodiment, a Peripheral Component Interconnect Express (PCIe) Input/Output (I/O) device operable to perform Single Root I/O Virtualization (SR-IOV) is provided. The device comprises hardware registers implementing a PCIe configuration space for the device, and firmware implementing one or more SR-IOV virtual functions that each provide a virtual machine access to a subset of PCIe configuration space hardware registers for the device. The device further includes a hardware recovery register directly accessible by each of the virtual machines, and a control unit. The control unit is operable to detect a firmware fault at the I/O device and to update the hardware recovery register with information describing the firmware fault.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: February 10, 2015
    Assignee: LSI Corporation
    Inventors: Moby J. Abraham, Parag R. Maharana
  • Publication number: 20140258595
    Abstract: A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logical devices and exposed to a resource allocator. A core caching algorithm executes in the guest virtual machine. As new virtual machines are added under the management of the virtual machine monitor, existing virtual machines are prompted to relinquish a portion of the cache store allocated for use by the respective existing machines. The relinquished cache is allocated to the new machine. Similarly, if a virtual machine is shutdown or migrated to a new host system, the cache capacity allocated to the virtual machine is redistributed among the remaining virtual machines being managed by the virtual machine monitor.
    Type: Application
    Filed: August 15, 2013
    Publication date: September 11, 2014
    Applicant: LSI Corporation
    Inventors: Pradeep Radhakrishna Venkatesha, Siddhartha Kumar Panda, Parag R. Maharana, Luca Bert
  • Publication number: 20140244936
    Abstract: Systems and methods maintain cache coherency between storage controllers utilizing bitmap data. In one embodiment, a storage controller processes an I/O request for a logical volume from a host, and generates one or more cache entries in a cache memory that is based on the request. The storage controller identifies a backup storage controller for managing the logical volume, and generates bitmap data that identifies cache entries in the cache memory that have changed since synchronizing with the backup storage controller. The storage controller provides the bitmap data to the backup storage controller to allow the backup storage controller to synchronize its cache memory with the cache memory of the storage controller based on the bitmap data.
    Type: Application
    Filed: August 19, 2013
    Publication date: August 28, 2014
    Applicant: LSI CORPORATION
    Inventors: Parag R. Maharana, Pradeep R. Venkatesha, Nagesh B. Kollipara, Subburaj Ramasamy, Nithin Surendran
  • Publication number: 20140237163
    Abstract: Methods and structure are provided for reducing the number of writes to a cache of a storage controller. One exemplary embodiment includes a storage controller that has a non-volatile flash cache memory, a primary memory that is distinct from the cache memory, and a memory manager. The memory manager is able to receive data for storage in the cache memory, to generate a hash key from the received data, and to compare the hash key to hash values for entries in the cache memory. The memory manager can write the received data to the cache memory if the hash key does not match one of the hash values. Also, the memory manager can modify the primary memory instead of writing to the cache if the hash key matches a hash value, in order to reduce the amount of data written to the cache memory.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: LSI CORPORATION
    Inventor: Parag R. Maharana
  • Publication number: 20140229769
    Abstract: In one embodiment, a Peripheral Component Interconnect Express (PCIe) Input/Output (I/O) device operable to perform Single Root I/O Virtualization (SR-IOV) is provided. The device comprises hardware registers implementing a PCIe configuration space for the device, and firmware implementing one or more SR-IOV virtual functions that each provide a virtual machine access to a subset of PCIe configuration space hardware registers for the device. The device further includes a hardware recovery register directly accessible by each of the virtual machines, and a control unit. The control unit is operable to detect a firmware fault at the I/O device and to update the hardware recovery register with information describing the firmware fault.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Applicant: LSI CORPORATION
    Inventors: Moby J. Abraham, Parag R. Maharana
  • Publication number: 20140229941
    Abstract: A method and controller device for sharing computing resources in a virtualized environment having a plurality of virtual machines. The method includes assigning a portion of the computing resources to the plurality of virtual machines. The method also includes leasing by a first virtual machine at least a portion of the assigned computing resources of at least one second virtual machine. The first virtual machine leases computing resources from the at least one second virtual machine when the first virtual machine needs additional computing resources and at least a portion of the assigned computing resources of the at least one second virtual machine are not being used by the at least one second virtual machine.
    Type: Application
    Filed: February 14, 2013
    Publication date: August 14, 2014
    Applicant: LSI CORPORATION
    Inventors: Luca Bert, Parag R. Maharana
  • Publication number: 20140229658
    Abstract: Methods and structure are provided for cache load balancing in storage controllers that utilize Solid State Drive (SSD) caches. One embodiment is a storage controller of a storage system. The storage controller includes a host interface operable to receive Input and Output (I/O) operations from a host computer. The storage controller also includes a cache memory that includes an SSD. Further, the storage controller includes a cache manager that is distinct from the cache memory. The cache manager is able to determine physical locations in the multiple SSDs that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location. Further, the cache manager is able to trigger transmission of the stored I/O operations to storage devices of the storage system for processing.
    Type: Application
    Filed: February 14, 2013
    Publication date: August 14, 2014
    Applicant: LSI CORPORATION
    Inventors: Parag R. Maharana, Kishore K. Sampathkumar
  • Publication number: 20140201462
    Abstract: A method and system for managing a cache for a host machine is disclosed. The method includes: indicating each cache line in the cache as being in a transitional meta-state when any virtual machine hosted on the host machine moves out of the host machine; each time a particular cache line is accessed, indicating that particular cache line as no longer in the transitional meta-state; and marking the cache lines still in the transitional meta-state as invalid when a virtual machine moves back to the host machine.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 17, 2014
    Applicant: LSI CORPORATION
    Inventors: Parag R. Maharana, Luca Bert, Earl Cohen
  • Publication number: 20140025890
    Abstract: Methods and structure for improved flexibility in managing cache memory in a storage controller of a computing device on which multiple virtual machines (VMs) are operating in a VM computing environment. Embodiments hereof provide for the storage controller to receive configuration information from a VM management system coupled with the storage controller where the configuration information comprises information regarding each VM presently operating on the computing device. Based on the configuration information, the storage controller allocates and de-allocates segments of the cache memory of the storage controller for use by the various virtual machines presently operating on the computing device. The configuration information may comprise indicia of the number of VMs presently operating as well as performance metric threshold configuration information to allocate/de-allocate segments based on present performance of each virtual machine.
    Type: Application
    Filed: December 12, 2012
    Publication date: January 23, 2014
    Applicant: LSI Corporation
    Inventors: Luca Bert, Parag R. Maharana
  • Publication number: 20120102491
    Abstract: A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 26, 2012
    Applicant: LSI CORPORATION
    Inventor: Parag R. Maharana
  • Patent number: 7788420
    Abstract: A plurality of modes is provided for communicating between a host system and a peripheral storage system controller. A first communication mode may be selected from the plurality of communication modes based on a bit length required to communicate a physical address. During runtime, a switch from the first communication mode to a second communication mode may be performed in order to improve the efficiency of processing address requests at the storage system controller.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 31, 2010
    Assignee: LSI Corporation
    Inventors: Parag R. Maharana, Senthil M. Thangaraj, Gerald E. Smith