Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.

Abstract: Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.

Abstract: Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.

Abstract: A capacitor includes a first metal layer over a substrate, a second metal layer over the first metal layer, and first and second cells. Each cell is electrically coupled to first and second buses. Each cell includes first plurality and second plurality of fingers in the first metal layer, and third plurality and fourth plurality of fingers in the second metal layer. The first plurality of fingers extend in a first direction parallel to a top surface of the substrate and are electrically coupled to the first bus. The second plurality of fingers extend in the first direction and are electrically coupled to the second bus. The third plurality of fingers extend in a second direction parallel to the top surface of the substrate and are electrically coupled to the first bus. The second direction is different from the first direction. The fourth plurality of fingers extend in the second direction and are electrically coupled to the second bus.

Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Abstract: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

Abstract: Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.

Abstract: A voltage-controlled oscillator (VCO) includes an inductor-capacitor (LC) tank circuit, tuning circuitry, and a plurality of first varactors. The LC tank circuit is configured to produce an oscillating signal and is operable in a plurality of frequency bands. The tuning circuitry is configured to tune the LC tank circuit to operate in a first frequency band of the plurality of frequency bands based at least in part on a temperature of the VCO. The plurality of first varactors are coupled to the LC tank circuit for tuning the oscillating signal to a target frequency within the first frequency band based on a control voltage.

Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

Abstract: Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

Abstract: Electrical circuits and associated methods relate to duty cycle correction having a voltage controlled delay line VCDL controlled by an analog voltage and a digital command signal to generate a VCDLout signal. In an illustrative example, the analog voltage may be generated by an analog circuit, the analog circuit may include a reference voltage, a low-pass filter, an amplifier and a loop filter. In an illustrative example, the analog circuit may be controlled by an analog command signal. The analog command signal may be programmable applied on the analog circuit to produce the analog voltage. The digital command signal may be programmable to select desired delay band in the VCDL. The analog voltage and the digital command signal may be applied to the VCDL together to obtain a desired duty cycle.

Abstract: Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.

Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

Abstract: Methods and apparatus relate to a bidirectional differential interface having a voltage-mode transmit driver architecture formed of multiple selectively enabled slices for coarse output resistance impedance matching. In an illustrative example, the transmit driver may include a programmable resistance for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors, for example, to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors, for example, to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver may have programmable voltage swing on, for example, the upper and/or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied, for example, through common mode resistors for receive mode operations.

Abstract: An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.