Patents by Inventor Parag Upadhyaya
Parag Upadhyaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9214941Abstract: An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.Type: GrantFiled: August 30, 2013Date of Patent: December 15, 2015Assignee: XILINX, INC.Inventors: Aman Sewani, Parag Upadhyaya
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Patent number: 9148192Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.Type: GrantFiled: August 8, 2013Date of Patent: September 29, 2015Assignee: XILINX, INC.Inventors: Alan C. Wong, Christopher J. Borrelli, Loren Jones, Seu Wah Low, Parag Upadhyaya, Robert M. Ondris, Sarosh I. Azad
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Patent number: 9136690Abstract: A termination circuit configured to provide electrostatic discharge (ESD) protection is provided. Termination sub-circuits are coupled in parallel, each including respective pull-up and pull-down circuits. Each pull-up circuit has two transistors of a first type coupled in series between a data input and Vdd, a gate of one of the two transistors being coupled to a control input and a gate of the other one of the two transistors being coupled to a first enable input of the termination sub-circuit. Each pull-down circuit has two transistors of a second type coupled in series between the data input and Vss or ground, a gate of one of the two transistors being coupled to the control input and the gate of the other one of the two transistors being coupled to a second enable input of the termination sub-circuit.Type: GrantFiled: August 30, 2011Date of Patent: September 15, 2015Assignee: XILINX, INC.Inventors: Parag Upadhyaya, Mark J. Marlett
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Publication number: 20150061756Abstract: An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Xilinx, Inc.Inventors: Aman Sewani, Parag Upadhyaya
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Patent number: 8941974Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.Type: GrantFiled: September 9, 2011Date of Patent: January 27, 2015Assignee: Xilinx, Inc.Inventors: Zhaoyin D. Wu, Parag Upadhyaya, Xuewen Jiang
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Patent number: 8860180Abstract: An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.Type: GrantFiled: October 26, 2012Date of Patent: October 14, 2014Assignee: Xilinx, Inc.Inventors: Jing Jing, Shuxian Wu, Parag Upadhyaya
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Patent number: 8841948Abstract: An apparatus relates generally to an injection-controlled-locked phase-locked loop (“ICL-PLL”) is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.Type: GrantFiled: March 14, 2013Date of Patent: September 23, 2014Assignee: Xilinx, Inc.Inventors: Jun-Chau Chien, Wayne Fang, Parag Upadhyaya, Jafar Savoj, Kun-Yung Chang
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Patent number: 8836391Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.Type: GrantFiled: October 2, 2012Date of Patent: September 16, 2014Assignee: Xilinx, Inc.Inventors: Parag Upadhyaya, Jafar Savoj, Anthony Torza
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Patent number: 8717115Abstract: A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.Type: GrantFiled: January 13, 2012Date of Patent: May 6, 2014Assignee: Xilinx, Inc.Inventor: Parag Upadhyaya
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Patent number: 8710883Abstract: An apparatus comprises a lock-loop circuit including an oscillator, a frequency detector, a charge pump, and a regulator. The regulator is coupled to provide a regulated signal to the oscillator to control frequency. The oscillator and the frequency detector are coupled to receive a reference clock signal. The reference clock signal is coupled to the oscillator to suppress noise in the oscillator by pulse injection. The frequency detector is coupled to receive an oscillator output from the oscillator.Type: GrantFiled: September 28, 2012Date of Patent: April 29, 2014Assignee: Xilinx, Inc.Inventors: Wayne Fang, Parag Upadhyaya
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Patent number: 8686539Abstract: A shielded inductor in an integrated circuit includes conductive loops disposed on a deep-well noise shield for isolating a noise coupling between the conductive loops and the substrate of the integrated circuit. The deep-well noise shield includes a first well disposed within a second well that is disposed within the substrate of the integrated circuit. The second well includes a peripheral well, a deep-well layer, and slot wells. The peripheral well surrounds a periphery of the first well. The peripheral well and the deep-well layer are coupled together to provide two p-n junctions that separate the first well and the substrate. The slot wells are distributed inside the periphery of the first well. Each slot well and the deep-well layer are coupled together. Each slot well has a width and a length that is at least three times the width.Type: GrantFiled: October 15, 2010Date of Patent: April 1, 2014Assignee: Xilinx, Inc.Inventors: Vassili Kireev, Parag Upadhyaya, Toan D. Tran
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Patent number: 8592943Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.Type: GrantFiled: March 21, 2011Date of Patent: November 26, 2013Assignee: Xilinx, Inc.Inventors: Zhaoyin D. Wu, Xuewen Jiang, Parag Upadhyaya
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Publication number: 20130181783Abstract: A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.Type: ApplicationFiled: January 13, 2012Publication date: July 18, 2013Applicant: XILINX, INC.Inventor: Parag Upadhyaya
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Publication number: 20130063861Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: XILINX, INC.Inventors: Zhaoyin D. Wu, Parag Upadhyaya, Xuewen Jiang
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Patent number: 8358192Abstract: A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.Type: GrantFiled: May 3, 2012Date of Patent: January 22, 2013Assignee: Xilinx, Inc.Inventors: Vassili Kireev, Parag Upadhyaya, Mark J. Marlett
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Publication number: 20120241904Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: XILINX, INC.Inventors: Zhaoyin D. Wu, Xuewen Jiang, Parag Upadhyaya
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Patent number: 8269566Abstract: A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.Type: GrantFiled: October 15, 2010Date of Patent: September 18, 2012Assignee: Xilinx, Inc.Inventors: Parag Upadhyaya, Vassili Kireev
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Publication number: 20120212315Abstract: A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.Type: ApplicationFiled: May 3, 2012Publication date: August 23, 2012Applicant: XILINX, INC.Inventors: Vassili Kireev, Parag Upadhyaya, Mark J. Marlett
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Publication number: 20120092119Abstract: A symmetrical inductor includes pairs of half-loops, first and second terminal electrodes, and a center-tap electrode. The half-loop pairs are in respective conductive layers of an integrated circuit. Each half-loop pair includes a first and second half-loop in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: XILINX, INC.Inventors: Vassili Kireev, Parag Upadhyaya, Mark J. Marlett
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Publication number: 20120092081Abstract: A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: XILINX, INC.Inventors: Parag Upadhyaya, Vassili Kireev