Abstract: A method for fabricating high aspect ratio nanostructures in arbitrary functional materials. An (N+1)th layer of substrate material is deposited on top of existing N layers of nanostructures, where N is a natural number. The substrate material in the (N+1)th layer is then patterned and etched to create complementary nanostructures in the substrate material. Furthermore, a conformal coating of gap-fill materials, encapsulation layers, and functional material on the complementary nanostructures is performed to create functional material nanostructures in the (N+1)th layer. A set of selective etches on the substrate material is then performed leaving behind multi-layered high aspect ratio nanostructures in the functional material.

Abstract: A system and method for thinning a group of two or more dies. An etch gas chemistry is introduced into a plasma generator. Furthermore, plasma is generated using the etch gas chemistry by the plasma generator. The two or more dies placed within an etch chamber are then etched to thin the two or more dies until the two or more dies achieve a desired thickness using the plasma. Furthermore, a spatially variable closed loop control of etch rates of the etching is implemented to provide spatially variable etch rates during the thinning of the two or more dies.

Abstract: A method for implementing high-precision heterogeneous integration. An etch of a first bonding surface and a second bonding surface is performed to create nanostructures in the first bonding surface and/or the second bonding surface. The first and second bonding surfaces are bonded together, where a particle lands at a bonding interface resulting in an exclusion zone that is at least two times smaller than a bonding of two bonding surfaces with no nanostructures.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A system for assembling a group of dies from a source substrate onto a transfer substrate. A high-throughput low-precision system is configured to pick the group of dies from the source substrate and placed onto an intermediate substrate, where the placement of the group of dies onto the intermediate substrate is performed such that the X and/or Y pitch of the placed group of dies matches a corresponding system-in-package (SiP) pitch. Furthermore, a parallel high-precision system is configured to pick and place the group of dies from the intermediate substrate onto the transfer substrate, where the placement of the group of dies onto the transfer substrate is performed at the SiP pitch, where a precision of assembly onto the transfer substrate is sub-500 nm.

Abstract: A system for assembling a first substrate to a second substrate. One or more deformable substrate chucks are utilized to match a topography of a bonding surface on the first substrate to a topography of a bonding surface on the second substrate, where a volatile lubricant is utilized during an alignment step.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method and system for etching a semiconductor substrate using catalyst influenced chemical etching. A group of independently controlled discrete actuators are configured to control a depth of an etch of a material on a substrate, where at least two of the group of independently controlled discrete actuators has distinct actuation values. Furthermore, the etch depth has a variation of less than 10% of a feature height across the substrate.

Abstract: A diagnostic chip for detecting biomarkers and trace amounts of nanoparticles in chemical mixtures or in water. The diagnostic chip includes one or more inputs, where a sample containing differently sized particles is introduced into at least one of these inputs. Furthermore, the diagnostic chip includes multiple separation regions, where the sample is pressurized as it passes through the separation regions. Each separation region includes a deterministic lateral displacement array, where the deterministic lateral displacement array in two or more of these separation regions has a different etch depth profile. In this manner, the diagnostic chip effectively detects biomarkers and trace amounts of nanoparticles in chemical mixtures or in water.

Abstract: A method for bonding with precision alignment. A first bonding surface is bonded with a second bonding surface, where features on the first and second bonding surfaces are precisely overlaid during the bonding. An etch is then performed on the first and/or second bonding surfaces to create recesses in the first and/or second bonding surfaces. Precision alignment of the first and second bonding surfaces is then enabled by a volatile fluid deployed between the first and second bonding surfaces, where the recesses enable removal of the volatile fluid from a bonding interface during and after the bonding.

Abstract: A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

Abstract: A method for fabricating silicon nanostructures. An etch uniformity improving layer is deposited on a substrate. A catalyst (e.g., thin film of Ti/Au) is deposited on the substrate or the etch uniformity improving layer, where the catalyst is contacting a portion of the substrate or the etch uniformity layer. The catalyst and the substrate or etch uniformity improving layer are exposed to an etchant, where the catalyst causes etching of the substrate thereby creating etched nanostructures.

Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).