Patents by Inventor Park Kim

Park Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072020
    Abstract: A semiconductor package may include a lower structure, a first semiconductor chip on the lower structure, the first semiconductor chip including a hot spot, a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the lower structure, and a connection chip in the lower structure and connecting the first and second semiconductor chips to each other. The hot spot may vertically overlap the connection chip.
    Type: Application
    Filed: March 23, 2023
    Publication date: February 29, 2024
    Inventors: JAE CHOON KIM, Hwanjoo PARK, Sunggu KANG, SUNG-HO MUN
  • Publication number: 20240066707
    Abstract: An apparatus for automatically fastening a chemical coupler to a connector of an automatic clean quick coupler (ACQC) system, includes a main body, a multi-degree of freedom (DOF) robot arm on the main body, a gripper on the multi-DOF robot arm that is configured to grip the chemical coupler, a vision sensor on the multi-DOF robot arm, and a controller connected to the gripper, the multi-DOF robot arm, and the vision sensor. The controller uses information about an environment surrounding the multi-DOF robot arm acquired by the vision sensor, to control an operation of the multi-DOF robot arm and an operation of the gripper.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 29, 2024
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Industry-Academic Cooperation Foundation of Kyungnam University
    Inventors: Shibaek PARK, Han Sung KIM, Jooha MAENG, Youngsuk PARK, Gi Seong KIM, Sung Hun JEONG
  • Publication number: 20240074313
    Abstract: A compound represented by Chemical Formula 1, and near-infrared absorbing/blocking films, photoelectric devices, organic sensors, and electronic devices including the compound are provided: wherein, in Chemical Formula 1, X1 to X4, and R1 to R9 are the same as defined in the detailed description.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 29, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sangdong KIM, Sang Ho PARK, Rae Sung KIM, Insun PARK, Dong-Seok LEEM
  • Publication number: 20240069571
    Abstract: Provided is a method for controlling, in a space where a plurality of robots autonomously travel, the robots such that each of the plurality of robots can successively pass through a designated region, by identifying the designated region to be passed through by the robots and i) controlling the robots to pass through the corresponding designated region via a first point defined in the designated region or ii) triggering a designated region traveling mode of the robots and controlling the robots to pass through the corresponding designated region in the designated region traveling mode.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Younghwan YOON, Kay PARK, Jin Yong KIM, Jinyoung CHOI, Jung-eun KIM
  • Publication number: 20240071689
    Abstract: A method of manufacturing a multilayer electronic component includes forming a stack by stacking a plurality of ceramic green sheets on which conductive patterns are disposed on a support film, cutting the stack in a second direction, perpendicular to a first direction which is a stacking direction of the plurality of ceramic green sheets, cutting the stack in a third direction, perpendicular to the first and second directions, to obtain a plurality of unit chips, separating the unit chip from the support film, arranging the unit chip such that one of side surfaces of the unit chip is in contact with an adhesive tape, and attaching another one of the side surfaces to a ceramic green sheet for a side margin portion, and forming a side margin portion on the another one of side surfaces.
    Type: Application
    Filed: March 28, 2023
    Publication date: February 29, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Myung Chan SON, Yong PARK, Jong Ho LEE, Eun Jung LEE, Jung Tae PARK, Min Woo KIM, Ji Hyeon LEE, Sun Mi KIM
  • Patent number: 11914262
    Abstract: The present disclosure relates to a light shutter panel and a transparent display apparatus having the same. The light shutter panel comprises: a first light shutter panel and a second light shutter panel. Each of the first and second light shutter panels includes: a lower electrode plate, an upper electrode plate, a shutter layer, transparent spacers and a black ink. The lower electrode plate and the upper electrode plate are attached as facing each other. The shutter layer is disposed between the lower electrode plate and the upper electrode plate. The shutter layer includes a maximum light transmitting portion, a minimum light blocking portion, an ink storage portion and an electric field guide. The electric field guide is disposed between the ink storage portions. The transparent spacers maintain the gap between the lower electrode plate and the upper electrode plate. The black ink is filled into the ink storage portion.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: February 27, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Youngki Song, JaeHyun Park, Sun Man Kim
  • Patent number: 11912629
    Abstract: A method for enhancing mechanical properties of sintered, zirconia ceramic bodies and zirconia ceramic dental restorations is provided. A porous or pre-sintered stage of a ceramic body may be treated with a tantalum-containing composition prior to sintering. Alternatively, zirconia ceramic powder may be coated with a tantalum-containing composition prior to forming a shaped ceramic body. After sintering, the resulting ceramic bodies have enhanced mechanical properties, such as greater fracture toughness, without a significant decrease in optical properties.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: James R. Glidewell Dental Ceramics, Inc.
    Inventors: Jae Won Kim, Enoch Park
  • Patent number: 11917881
    Abstract: A display device includes light transmitting areas including a first light transmitting area and light emitting areas around the light transmitting areas and including a first light emitting area disposed around the first light transmitting area, wherein the first light emitting area includes a first-first light emitting area adjacent to a first portion of each of the light transmitting areas, a first-second light emitting area adjacent to a second portion of each of the light transmitting areas, a first-third light emitting area adjacent to a third portion of each of the light transmitting areas, and a first-fourth light emitting area disposed adjacent to a fourth portion of each of the light transmitting areas. The first-first to first-fourth light emitting areas each include at least one of first to third light emitting portions to emit light of first to third colors, respectively.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woong Hee Jeong, Ki Bum Kim, Jin Yeong Kim, Hyang A Park, Tae Hoon Yang, Jong Chan Lee
  • Patent number: 11914572
    Abstract: Technologies are described providing adaptive query routing in a replicated database environment. The technologies can be used with a variety of replication protocols. Prepared statements, such as for queries, from a database client can be routed to a source node, or a source node and available replica nodes, when a replica node becomes unavailable. When a replica node becomes available again, a prepared statement can be updated to indicate that the updated prepared statement can be executed at nodes including the replica node that is available again. Prepared statement routing can also be used when a portion of replicated data becomes unavailable at a replica node, but a portion of replicated data remains available.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: February 27, 2024
    Assignee: SAP SE
    Inventors: Juchang Lee, Kyu Hwan Kim, Joo Yeon Lee, Kyungyul Park, Deok Hoe Kim
  • Patent number: 11913923
    Abstract: A method for evaluating physical properties of a melt-blown plastic resin, and, more specifically, to a novel method for evaluating physical properties are provided. When a particular plastic resin is processed by a melt-blown process, a stretching diameter value after the process of the plastic resin can be accurately derived from a physical property value measured using a specimen of the resin.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: February 27, 2024
    Assignee: LG Chem, Ltd.
    Inventors: Hyunsup Lee, Seok Hwan Kim, Heekwang Park, Ki Soo Lee, Sangjin Jeon, Myunghan Lee
  • Publication number: 20190152312
    Abstract: A structure for a high-pressure vessel is provided to inhibit a gap between a plastic liner and a plastic sealing member due to the plastic sealing member being combined with the plastic liner by thermal bonding, thereby preventing the leakage of high-pressure gas to the gap between the plastic liner and the plastic sealing member. In addition, as the plastic liner and the plastic sealing member made of the same materials are combined with each other by the thermal bonding, use of the conventional lower fastening member is unnecessary, and further, use of a rubber sealing member for maintaining airtightness is unnecessary. Thus productivity via reduction in the number of components, a weight, a cost, and man-hours is improved.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Applicant: DONG HEE INDUSTRIAL CO., LTD.
    Inventors: Kyun Bum PARK, Hyung Joo CHO, Lee Park KIM, Tae Hong KYE
  • Patent number: 8938120
    Abstract: An image data processing method includes generating a data window comprising N rows and N columns using Bayer data from a pixel array, generating a red (R), green (G), blue (B) data of a center pixel in the data window, detecting an edge region in the data window, detecting a bright region in the data window, adjusting the R, G, B data using a suppressing gain factor if both of the edge region and bright region is detected, and outputting the adjusting R, G, B data as a result of an interpolating process.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: January 20, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Park Kim
  • Patent number: 8531529
    Abstract: A dead pixel compensating apparatus includes, inter alia, a pattern generation unit generating a programmable test pattern including data with respect to at least one dead pixel; a register array storing the test pattern; a dead pixel compensation unit receiving the test pattern stored in the register array and performing a dead pixel compensation algorithm to output compensation data; and a determination unit comparing the test pattern and the compensation data to determine whether or not the dead pixel compensation algorithm has an error, wherein a dead pixel compensation algorithm for compensating for a dead pixel of an image sensor in image data supplied from the image sensor is tested.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: September 10, 2013
    Assignee: SK Hynix Inc.
    Inventors: Geon Pyo Kim, Jong Park Kim, Myoung Kwan Kim
  • Patent number: 8406079
    Abstract: Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: March 26, 2013
    Assignee: SK Hynix Inc.
    Inventors: Young Park Kim, Duk Su Chun
  • Patent number: 8323466
    Abstract: A microfluidic-based lab-on-a-test card is described. The test card is used with a point-of-care (POC) analyzer. The test card is designed to receive a sample and then, with the use of the POC analyzer, quantify or count a particular substance in the sample. The test card may be comprised of multiple layers. In one embodiment, the test card includes a primary separation chamber with a filtration surface, a trapping channel, and a particle detector. The test card may also include a nanowire sensor.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: December 4, 2012
    Assignee: NanoIVD, Inc.
    Inventors: Sunnie Park Kim, Young Shik Shin, Changgeng Liu, Rory Kelly, Becky Chan
  • Publication number: 20120258445
    Abstract: Methods for using nanowire sensors are described. In one embodiment, the nanowire sensor may be field effect transistor having a nanowire and a functionalized control electrode. One method of using such a nanowire sensor includes exposing the functionalized control electrode to a test sample and an enhancing reagent. In another embodiment, the nanowire sensor may be a field effect transistor having a gate electrode and a functionalized nanowire. One method of using such a nanowire sensor includes exposing the functionalized nanowire to a test sample and an enhancing reagent. The use of an enhancing reagent increases the sensitivity of the nanowire sensor to a substance to be detected or quantified.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 11, 2012
    Applicant: NanolVD, Inc.
    Inventors: Sunnie Park KIM, Young Shik SHIN, Changgeng LIU
  • Publication number: 20120105648
    Abstract: A dead pixel compensating apparatus includes, inter alia, a pattern generation unit generating a programmable test pattern including data with respect to at least one dead pixel; a register array storing the test pattern; a dead pixel compensation unit receiving the test pattern stored in the register array and performing a dead pixel compensation algorithm to output compensation data; and a determination unit comparing the test pattern and the compensation data to determine whether or not the dead pixel compensation algorithm has an error, wherein a dead pixel compensation algorithm for compensating for a dead pixel of an image sensor in image data supplied from the image sensor is tested.
    Type: Application
    Filed: October 14, 2011
    Publication date: May 3, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Geon Pyo KIM, Jong Park KIM, Myoung Kwan KIM
  • Patent number: 8154019
    Abstract: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong Kee Kwon, Hyung Dong Lee, Young Park Kim
  • Publication number: 20110271133
    Abstract: Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal.
    Type: Application
    Filed: December 16, 2010
    Publication date: November 3, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Young Park Kim, Duk Su Chun
  • Publication number: 20110074369
    Abstract: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.
    Type: Application
    Filed: December 29, 2009
    Publication date: March 31, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Yong Kee KWON, Hyung Dong Lee, Young Park Kim