Abstract: A method for enhancing mechanical properties of sintered, zirconia ceramic bodies and zirconia ceramic dental restorations is provided. A porous or pre-sintered stage of a ceramic body may be treated with a tantalum-containing composition prior to sintering. Alternatively, zirconia ceramic powder may be coated with a tantalum-containing composition prior to forming a shaped ceramic body. After sintering, the resulting ceramic bodies have enhanced mechanical properties, such as greater fracture toughness, without a significant decrease in optical properties.

Abstract: A display device includes light transmitting areas including a first light transmitting area and light emitting areas around the light transmitting areas and including a first light emitting area disposed around the first light transmitting area, wherein the first light emitting area includes a first-first light emitting area adjacent to a first portion of each of the light transmitting areas, a first-second light emitting area adjacent to a second portion of each of the light transmitting areas, a first-third light emitting area adjacent to a third portion of each of the light transmitting areas, and a first-fourth light emitting area disposed adjacent to a fourth portion of each of the light transmitting areas. The first-first to first-fourth light emitting areas each include at least one of first to third light emitting portions to emit light of first to third colors, respectively.

Abstract: The present disclosure relates to a light shutter panel and a transparent display apparatus having the same. The light shutter panel comprises: a first light shutter panel and a second light shutter panel. Each of the first and second light shutter panels includes: a lower electrode plate, an upper electrode plate, a shutter layer, transparent spacers and a black ink. The lower electrode plate and the upper electrode plate are attached as facing each other. The shutter layer is disposed between the lower electrode plate and the upper electrode plate. The shutter layer includes a maximum light transmitting portion, a minimum light blocking portion, an ink storage portion and an electric field guide. The electric field guide is disposed between the ink storage portions. The transparent spacers maintain the gap between the lower electrode plate and the upper electrode plate. The black ink is filled into the ink storage portion.

Abstract: A method for evaluating physical properties of a melt-blown plastic resin, and, more specifically, to a novel method for evaluating physical properties are provided. When a particular plastic resin is processed by a melt-blown process, a stretching diameter value after the process of the plastic resin can be accurately derived from a physical property value measured using a specimen of the resin.

Abstract: A structure for a high-pressure vessel is provided to inhibit a gap between a plastic liner and a plastic sealing member due to the plastic sealing member being combined with the plastic liner by thermal bonding, thereby preventing the leakage of high-pressure gas to the gap between the plastic liner and the plastic sealing member. In addition, as the plastic liner and the plastic sealing member made of the same materials are combined with each other by the thermal bonding, use of the conventional lower fastening member is unnecessary, and further, use of a rubber sealing member for maintaining airtightness is unnecessary. Thus productivity via reduction in the number of components, a weight, a cost, and man-hours is improved.

Abstract: An image data processing method includes generating a data window comprising N rows and N columns using Bayer data from a pixel array, generating a red (R), green (G), blue (B) data of a center pixel in the data window, detecting an edge region in the data window, detecting a bright region in the data window, adjusting the R, G, B data using a suppressing gain factor if both of the edge region and bright region is detected, and outputting the adjusting R, G, B data as a result of an interpolating process.

Abstract: A dead pixel compensating apparatus includes, inter alia, a pattern generation unit generating a programmable test pattern including data with respect to at least one dead pixel; a register array storing the test pattern; a dead pixel compensation unit receiving the test pattern stored in the register array and performing a dead pixel compensation algorithm to output compensation data; and a determination unit comparing the test pattern and the compensation data to determine whether or not the dead pixel compensation algorithm has an error, wherein a dead pixel compensation algorithm for compensating for a dead pixel of an image sensor in image data supplied from the image sensor is tested.

Abstract: Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal.

Abstract: A microfluidic-based lab-on-a-test card is described. The test card is used with a point-of-care (POC) analyzer. The test card is designed to receive a sample and then, with the use of the POC analyzer, quantify or count a particular substance in the sample. The test card may be comprised of multiple layers. In one embodiment, the test card includes a primary separation chamber with a filtration surface, a trapping channel, and a particle detector. The test card may also include a nanowire sensor.

Abstract: Methods for using nanowire sensors are described. In one embodiment, the nanowire sensor may be field effect transistor having a nanowire and a functionalized control electrode. One method of using such a nanowire sensor includes exposing the functionalized control electrode to a test sample and an enhancing reagent. In another embodiment, the nanowire sensor may be a field effect transistor having a gate electrode and a functionalized nanowire. One method of using such a nanowire sensor includes exposing the functionalized nanowire to a test sample and an enhancing reagent. The use of an enhancing reagent increases the sensitivity of the nanowire sensor to a substance to be detected or quantified.

Abstract: A dead pixel compensating apparatus includes, inter alia, a pattern generation unit generating a programmable test pattern including data with respect to at least one dead pixel; a register array storing the test pattern; a dead pixel compensation unit receiving the test pattern stored in the register array and performing a dead pixel compensation algorithm to output compensation data; and a determination unit comparing the test pattern and the compensation data to determine whether or not the dead pixel compensation algorithm has an error, wherein a dead pixel compensation algorithm for compensating for a dead pixel of an image sensor in image data supplied from the image sensor is tested.

Abstract: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

Abstract: Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal.

Abstract: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

Abstract: A microfluidic-based lab-on-a-test card is described. The test card is used with a point-of-care (POC) analyzer. The test card is designed to receive a sample and then, with the use of the POC analyzer, quantify or count a particular substance in the sample. The test card may be comprised of multiple layers. In one embodiment, the test card includes a primary separation chamber with a filtration surface, a trapping channel, and a particle detector. The test card may also include a nanowire sensor.

Abstract: An apparatus may include a first phase control circuit and/or a second phase control circuit. The first phase control circuit may compare the phase of the first clock signal with the phase of the second clock signal, and may control the phase of the first clock signal based on the result of the comparison. The second phase control circuit may control the phase of the second clock signal based on the result of the comparison output from the first phase control circuit. The first phase control circuit may control the phase of the first clock signal and/or the second phase control circuit may control the phase of the second clock signal such that they are synchronized with each other.

Abstract: A memory controller and a semiconductor device comprising the same are provided. The semiconductor device comprises a memory block comprising a plurality of memory banks and a memory controller. The memory controller outputs an auto refresh command and memory bank information indicating a memory bank that is to be auto refreshed in an auto refresh mode. Thus, only the selected memory bank performs an auto refresh operation in the auto refresh mode while reducing current consumption in the semiconductor device.

Abstract: A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock.

Abstract: A multiport memory device includes a first dedicated memory region, a second dedicated memory region, and a shared memory region. The first dedicated memory region can be accessed by a first, processor. The second dedicated memory region can be accessed fay a second processor. The shared memory region can be accessed by both the first processor and the second processor. The shared memory region and comprises an SRAM.

Abstract: A delay signal generator circuit is provided. A delay circuit including a plurality of series-connected inverters for sequentially delaying a first clock signal and for generating a plurality of delay signals and a multiplexer for selecting one of the delay signals. A delay control circuit samples the selected delay signal in response to a transition of a second clock signal. The second clock signal has twice the frequency of the first clock signal, and the delay control circuit controls the delay circuit based upon the sampled value(s) so that the selected delay signal output from the delay circuit has a delay time of ¼ clock cycle relative to the first clock signal.