Patents by Inventor Pascal A. MEINERZHAGEN
Pascal A. MEINERZHAGEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343389Abstract: An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.Type: ApplicationFiled: April 25, 2022Publication date: October 26, 2023Inventors: Gururaj Shamanna, Naveen Kumar, Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen
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Publication number: 20230123514Abstract: Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.Type: ApplicationFiled: October 18, 2021Publication date: April 20, 2023Inventors: Gururaj K. Shamanna, Naveen Kumar M., Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen, Sravan K. Puchakayala, Iqbal Rajwani
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Publication number: 20220091652Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).Type: ApplicationFiled: December 19, 2020Publication date: March 24, 2022Applicant: Intel CorporationInventors: Charles Augustine, Pascal Meinerzhagen, Suyoung Bang, Abdullah Afzal, Karthik Subramanian, Muhammad Khellah, Arvind Raman
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Patent number: 11079830Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.Type: GrantFiled: May 24, 2016Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Yong Shim, Pascal A. Meinerzhagen
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Patent number: 10908673Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.Type: GrantFiled: February 7, 2018Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Pascal Meinerzhagen, Stephen Kim, Dongmin Yoon, Minki Cho, Muhammad Khellah
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Patent number: 10784865Abstract: A minimum delay error apparatus such as a minimum delay error detection, prediction, correction, repair, prevention, and/or avoidance apparatus includes a minimum delay path replica circuit. The minimum delay path replica circuit can detect or predict, and subsequently can correct or avoid, minimum delay errors in data paths of digital circuits using pulsed latches.Type: GrantFiled: May 15, 2019Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Pascal Meinerzhagen, Vivek De, Muhammad Khellah
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Patent number: 10511224Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.Type: GrantFiled: April 3, 2018Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Patent number: 10483961Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.Type: GrantFiled: March 19, 2018Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Muhammad Khellah
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Patent number: 10454476Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.Type: GrantFiled: September 28, 2018Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Suyoung Bang, Muhammad Khellah, Charles Augustine, Pascal Meinerzhagen, Minki Cho
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Publication number: 20190288681Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.Type: ApplicationFiled: March 19, 2018Publication date: September 19, 2019Inventors: Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Muhammad Khellah
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Patent number: 10418076Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.Type: GrantFiled: September 15, 2017Date of Patent: September 17, 2019Assignee: Intel CorporationInventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
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Patent number: 10410699Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.Type: GrantFiled: June 29, 2018Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Anupama A. Thaploo, Bhushan Borole, Muhammad M. Khellah, Pascal A. Meinerzhagen
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Publication number: 20190243440Abstract: An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Applicant: Intel CorporationInventors: Pascal Meinerzhagen, Stephen Kim, Dongmin Yoon, Minki Cho, Muhammad Khellah
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Patent number: 10333379Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.Type: GrantFiled: December 16, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Suphachai Chai Sutanthavibul, Iqbal Rajwani, Anupama A Thaploo, Surya Sasi Kiran Tallapragada, Daivik H Bhatt, Lei Jiang, Stephen Kim, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Patent number: 10243563Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.Type: GrantFiled: December 29, 2016Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Andrea Bonetti, Jaydeep P. Kulkarni, Carlos Tokunaga, Minki Cho, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Publication number: 20190044512Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.Type: ApplicationFiled: September 28, 2018Publication date: February 7, 2019Inventors: Suyoung Bang, Muhammad Khellah, Charles Augustine, Pascal Meinerzhagen, Minki Cho
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Publication number: 20180226887Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Publication number: 20180191347Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Andrea Bonetti, Jaydeep P. Kulkarni, Carlos Tokunaga, Minki Cho, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Patent number: 10014767Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.Type: GrantFiled: March 25, 2016Date of Patent: July 3, 2018Assignee: Intel CorporationInventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Publication number: 20180175832Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Suphachai Chai Sutanthavibul, Iqbal Rajwani, Anupama A. Thaploo, Surya Sasi Tallapragada, Daivik H. Bhatt, Lei Jiang, Stephen Kim, Pascal A. Meinerzhagen, Muhammad M. Khellah