Patents by Inventor Pascal A. MEINERZHAGEN

Pascal A. MEINERZHAGEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12367926
    Abstract: Circuits for optimizing the duration of a sense amp enable signal in a memory device such as SRAM.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: July 22, 2025
    Assignee: Intel Corporation
    Inventors: Gururaj K. Shamanna, Naveen Kumar M., Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen, Sravan K. Puchakayala, Iqbal Rajwani
  • Publication number: 20250209221
    Abstract: Systems and methods for providing standard cell yield information in a library (i.e., creating “defect-aware” libraries). The method includes accessing a library of a plurality of standard cells characterized on a foundry process node and revision. A geometric analysis is performed on individual ones of the standard cells to identify potential defects, such as shorts and opens. A defect is injected (i.e., “realized” or “actualized”) at the location of the identified potential defects. The standard cells in the library are then simulated with the defects injected to generate simulated yield information. Additionally, methods can access silicon failure analysis data representing test chips designed with the library and generate an inferred failure rate for the individual standard cells in the library, as a function of the silicon failure analysis and the simulated yield information.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Intel Corporation
    Inventors: Srikanth Venkat Raman, Pascal A. Meinerzhagen, Andrew Radcliffe, Jimmy Voong Liu, Jay Gandhi, Muhammad M. Khellah
  • Publication number: 20230343389
    Abstract: An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1->0) ST CLK # based on PCLK assertion (0->1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: Gururaj Shamanna, Naveen Kumar, Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen
  • Publication number: 20230123514
    Abstract: Embodiments herein relate to optimizing the duration of a sense amp enable signal in a memory device such as SRAM. A control circuit asserts the sense amp enable signal in response to a clock signal from a replica column of the SRAM. A feedback path extends from the sense amps back to the control circuit. In one approach, a change in a feedback signal on the feedback path indicates the sense amps have all received the sense amp enable signal. In another approach, a change in a feedback signal on the feedback path indicates the sense amps have all completed their sensing operations. In some cases, a selection can be made among multiple feedback paths.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 20, 2023
    Inventors: Gururaj K. Shamanna, Naveen Kumar M., Jagadeesh Chandra Salaka, Pascal A. Meinerzhagen, Sravan K. Puchakayala, Iqbal Rajwani
  • Patent number: 11079830
    Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Yong Shim, Pascal A. Meinerzhagen
  • Patent number: 10511224
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 10418076
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
  • Patent number: 10410699
    Abstract: Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first mode of the apparatus, a second input node to receive second information during a second mode of the apparatus, a first clock node to receive a first signal, a second clock node to receive a second signal, a third clock node to receive a third signal, and a fourth clock node to receive a fourth signal; a first conductive connection coupled between an output node of a first latch among the latches and the first input node of a second latch among the latches; a second conductive connection coupled between an output node of the second latch and the first input node of a third latch among the latches; and a third conductive connection coupled between an output node of the third latch and the first input node of a fourth latch among the latches.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Anupama A. Thaploo, Bhushan Borole, Muhammad M. Khellah, Pascal A. Meinerzhagen
  • Patent number: 10333379
    Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Suphachai Chai Sutanthavibul, Iqbal Rajwani, Anupama A Thaploo, Surya Sasi Kiran Tallapragada, Daivik H Bhatt, Lei Jiang, Stephen Kim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 10243563
    Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Andrea Bonetti, Jaydeep P. Kulkarni, Carlos Tokunaga, Minki Cho, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Publication number: 20180226887
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Publication number: 20180191347
    Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Andrea Bonetti, Jaydeep P. Kulkarni, Carlos Tokunaga, Minki Cho, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 10014767
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Publication number: 20180175832
    Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Suphachai Chai Sutanthavibul, Iqbal Rajwani, Anupama A. Thaploo, Surya Sasi Tallapragada, Daivik H. Bhatt, Lei Jiang, Stephen Kim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 9948179
    Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Pascal A. Meinerzhagen, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Publication number: 20180024761
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 25, 2018
    Inventors: Pascal A. MEINERZHAGEN, Stephen T. KIM, Anupama A. THAPLOO, Muhammad M. KHELLAH
  • Publication number: 20170344090
    Abstract: Described is an apparatus which comprises: a controllable power gate coupled to an ungated power supply node and a gated power supply node; and a charge-pump circuit operable to be turned on and off according to a logic, wherein the charge pump circuit is coupled in parallel to the controllable power gate and also coupled to the ungated power supply node and the gated power supply node.
    Type: Application
    Filed: May 24, 2016
    Publication date: November 30, 2017
    Inventors: Jaydeep P. Kulkarni, Yong Shim, Pascal A. Meinerzhagen
  • Publication number: 20170279348
    Abstract: Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Jaydeep Kulkarni, Yong Shim, Pascal A. Meinerzhagen, Muhammad M. Khellah
  • Patent number: 9766827
    Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Pascal A. Meinerzhagen, Stephen T. Kim, Anupama A. Thaploo, Muhammad M. Khellah
  • Patent number: 9755631
    Abstract: Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate transistor having a gate terminal; a resistive device; a first transistor coupled in series with the resistive device together forming a pair, the first transistor also coupled to the gate terminal of the power gate transistor; a capacitive device coupled in parallel to the series coupled pair of the first transistor and resistive device; and a second transistor coupled to the gate terminal of the power gate transistor and the ungated power supply node.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Yong Shim, Jaydeep P. Kulkarni, Pascal A. Meinerzhagen, Muhammad M. Khellah