Patents by Inventor Pascal Chevalier
Pascal Chevalier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210057520Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.Type: ApplicationFiled: August 17, 2020Publication date: February 25, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20210057521Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.Type: ApplicationFiled: August 17, 2020Publication date: February 25, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20200411381Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
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Publication number: 20200411382Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
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Patent number: 10618465Abstract: A vehicle, in particular road vehicle, luminous glazing unit includes a laminated glazing unit and a first light source at the periphery of the glazing unit, a luminous woven textile including warp yarns, weft yarns and optical fibers, the optical fibers being capable of emitting light sideways, the optical fibers protruding from a first edge face of the laminated glazing unit, and the light source is connected to the first free ends of the optical fibers. The woven textile has openings between the warp yarns, the weft yarns and the optical fibers, lets a fraction of the solar radiation through via the openings and has a clarity C of at least 75%. The luminous woven textile is in optical contact with the faces F2 and F3 of the glass panes of the laminated glazing unit.Type: GrantFiled: September 9, 2016Date of Patent: April 14, 2020Assignee: SAINT-GOBAIN GLASS FRANCEInventors: Jean-Yves Laluet, Pascal Bauerle, Emmanuelle Artzner, Cédric Brochier, Delphine Chevalier
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Publication number: 20200111889Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.Type: ApplicationFiled: October 2, 2019Publication date: April 9, 2020Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis GAUTHIER, Pascal CHEVALIER
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Publication number: 20200111890Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.Type: ApplicationFiled: October 2, 2019Publication date: April 9, 2020Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis GAUTHIER, Pascal CHEVALIER
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Publication number: 20200013856Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal CHEVALIER, Alexis GAUTHIER
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Patent number: 10468508Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: GrantFiled: January 17, 2019Date of Patent: November 5, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Patent number: 10453919Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: GrantFiled: November 6, 2017Date of Patent: October 22, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Alexis Gauthier
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Patent number: 10381269Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.Type: GrantFiled: March 5, 2018Date of Patent: August 13, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Gregory Avenier
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Patent number: 10374069Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.Type: GrantFiled: December 13, 2017Date of Patent: August 6, 2019Assignee: STMicroelectronics SAInventor: Pascal Chevalier
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Publication number: 20190148531Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: ApplicationFiled: January 17, 2019Publication date: May 16, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20190140072Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: ApplicationFiled: November 6, 2017Publication date: May 9, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Alexis Gauthier
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Patent number: 10224423Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: GrantFiled: October 13, 2017Date of Patent: March 5, 2019Assignee: STMircoelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Publication number: 20180197781Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Gregory Avenier
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Publication number: 20180108762Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.Type: ApplicationFiled: December 13, 2017Publication date: April 19, 2018Applicant: STMicroelectronics SAInventor: Pascal Chevalier
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Patent number: 9941170Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.Type: GrantFiled: March 6, 2017Date of Patent: April 10, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Gregory Avenier
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Patent number: 9882034Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening having sidewalls lined with an insulating sheath. A portion of the insulating sheath adjacent the base region is removed and a base contact region is formed by epitaxial material grown from a portion of the base region exposed by removal of the portion of the insulating sheath.Type: GrantFiled: July 27, 2016Date of Patent: January 30, 2018Assignee: STMicroelectronics SAInventor: Pascal Chevalier
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Publication number: 20180025945Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.Type: ApplicationFiled: March 6, 2017Publication date: January 25, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Gregory Avenier