Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510503
    Abstract: Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: December 17, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat
  • Patent number: 10490632
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Patent number: 10475713
    Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20190310389
    Abstract: A method of operating a mechanical switching device is disclosed. The switching device includes a housing, an assembly disposed in the housing, and a body. The assembly is thermally deformable and comprises a beam held in two different places by two arms secured to edges of the housing. The beam is remote from the body in a first configuration and in contact with and immobilized by the body in a second configuration. The assembly has the first configuration at a first temperature and the second configuration when one of the arms has a second temperature different from the first temperature. The method includes exposing an arm of the assembly to the second temperature, and releasing the beam using a release mechanism. The release mechanism includes a pointed element comprising a pointed region directed towards the body. The pointed element limits an open crater in a concave part of a projection.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Publication number: 20190295965
    Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 26, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 10388695
    Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10379254
    Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 13, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Patent number: 10317846
    Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20190172785
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 6, 2019
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20190165105
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 30, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem BOUTON, Pascal FORNARA, Christian RIVERO
  • Patent number: 10283648
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 7, 2019
    Assignee: STMicroelectronic (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20190122845
    Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Christian Rivero, Pascal Fornara, Antonio Di-Giacomo, Brice Arrazat
  • Publication number: 20190113897
    Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 18, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • Publication number: 20190103369
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Pascal FORNARA, Guilhem BOUTON, Mathieu LISART
  • Patent number: 10249679
    Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 2, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10242944
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10211291
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Publication number: 20190027565
    Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Guilhem BOUTON, Pascal FORNARA, Julien DELALLEAU
  • Patent number: 10177101
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Patent number: 10157720
    Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: December 18, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat