Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272509
    Abstract: Methods of operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 8, 2025
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio Di-Giacomo, Brice Arrazat
  • Publication number: 20250015016
    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
    Type: Application
    Filed: September 17, 2024
    Publication date: January 9, 2025
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Publication number: 20240387328
    Abstract: A method for manufacturing a semiconductor device includes depositing a first protective layer over a first conductive feature and a second conductive feature. The first protective layer covers respective sidewalls and top surfaces of the first conductive feature and the second conductive feature. A portion of the first protective layer between the first conductive feature and the second conductive feature is removed. After removing the portion of the first protective layer, an intermetal dielectric layer is formed between the first conductive feature and the second conductive feature.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Pascal Fornara, Antonin Chollet, Julien Amouroux
  • Publication number: 20240379415
    Abstract: The present disclosure relates to a method for manufacturing a contact on a semiconductor region of an electronic component. The method includes forming a coating layer of dielectric material, with a thickness, on at least one side wall of an opening crossing through a dielectric region of the electronic component along a longitudinal direction from a first surface of the dielectric region, and opening out at the semiconductor region.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 14, 2024
    Inventors: Pascal Fornara, Christian Rivero, Julien Amouroux, Antonin Chollet
  • Patent number: 12125808
    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: October 22, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 12119310
    Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: October 15, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20240312977
    Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Roberto SIMOLA
  • Publication number: 20240292610
    Abstract: A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.
    Type: Application
    Filed: February 24, 2024
    Publication date: August 29, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Pascal FORNARA
  • Patent number: 12021074
    Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 25, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Roberto Simola
  • Patent number: 11906332
    Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20230326883
    Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak MARZAKI, Pascal FORNARA
  • Publication number: 20230326885
    Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • Publication number: 20230317637
    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Publication number: 20230260835
    Abstract: A method of manufacturing a contact on a semiconductor region includes a step of forming a stack of layers on lateral walls and at a bottom of an orifice (aligned with the semiconductor region) crossing a dielectric region along a longitudinal direction. The step of forming step is carried out from a first surface of the dielectric region and includes forming a polysilicon layer and a layer of a first metal in contact with the polysilicon layer. The first metal is preferably a metal selected from the group of transition metals and is well suited to forming with the polysilicon layer a metal silicide. The method further includes a step of performing thermal anneal causing a reaction between the first metal and the polysilicon layer to produce a layer of metal silicide. At least a portion of that layer of metal silicide extends in the longitudinal direction of the orifice.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 17, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Pascal FORNARA
  • Patent number: 11721647
    Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 8, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 11721646
    Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: August 8, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Patent number: 11715705
    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: August 1, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20230223448
    Abstract: A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 13, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Christian RIVERO, Franck JULIEN
  • Publication number: 20230154975
    Abstract: A PIN diode includes a first polycrystalline silicon region doped with a P-type of conductivity, a second polycrystalline silicon region doped with an N-type of conductivity and an intrinsic polycrystalline silicon region. At least the intrinsic polycrystalline silicon region is configured to include fluorine atoms. A polycrystalline silicon bar may include the first polycrystalline silicon region, the second polycrystalline silicon region and the intrinsic polycrystalline silicon region. The polycrystalline silicon bar may be supported by an insulating region within a semiconductor substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • Publication number: 20230085284
    Abstract: A method for detecting orientation of an integrated circuit is disclosed. The method includes moving, in response to a gravitational force, a mobile metallic piece in an evolution zone of a housing. The housing is formed in an interconnect region of the integrated circuit. The housing includes walls defining the evolution zone. The walls are formed within multiple metallization levels of the interconnect region. The walls include a floor wall and a ceiling wall. At least one of the floor wall and ceiling wall incorporate a pointed element directing its pointed region towards the mobile metallic piece. The pointed element delimits an open crater in a concave part of a projection. The method further includes creating an electrical signal by movement of the mobile metallic piece at a plurality of electrically conducting elements positioned at boundary points of the evolution zone and detecting the electrical signal by a detector.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 16, 2023
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara