Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 10211291
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • MOS TRANSISTOR WITH REDUCED HUMP EFFECT
    Publication number: 20190027565
    Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.
    Type: Application
    Filed: July 17, 2018
    Publication date: January 24, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Guilhem BOUTON, Pascal FORNARA, Julien DELALLEAU
  • Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit
    Patent number: 10177101
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: January 8, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Integrated mechanical device with vertical movement
    Patent number: 10157720
    Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: December 18, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat
  • INTEGRATED FUSE DEVICE
    Publication number: 20180254353
    Abstract: A fuse device is formed by a PN junction semiconducting region that is electrically insulated from other portions of an integrated circuit. The fuse device includes a first semiconducting zone having P type of conductivity and a second semiconducting zone having N type of conductivity in contact at a PN junction. First and second electrically conducting contact zones are provided on the first and second semiconducting zone, respectively, without making contact with the PN junction. One of the first and second semiconducting zones is configured with a non-homogeneous concentration of dopants, where a region with a lower value of concentration of dopant is located at the PN junction and a region with a higher value of concentration of dopant is locates at the corresponding electrically conducting contact zone.
    Type: Application
    Filed: September 14, 2017
    Publication date: September 6, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit
    Patent number: 10049982
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit
    Patent number: 10049991
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 14, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • Integrated electrical-switching mechanical device having a blocked state
    Patent number: 10026563
    Abstract: An integrated circuit, comprising an electrical-switching mechanical device in a housing having at least one first thermally deformable assembly including a beam held in at least two different locations by at least two arms secured to edges of the housing, the beam and the arms being metallic and situated within the same first metallization level and an electrically conductive body, wherein the said first thermally deformable assembly has at least one first configuration at a first temperature and a second configuration when at least one is at a second temperature different from the first temperature, wherein the beam is at a distance from the body in the first configuration and in contact with the said body and immobilized by the said body in the second configuration and establishing or prohibiting an electrical link passing through the body and through the beam.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 17, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Antonio Di-Giacomo, Christian Rivero, Pascal Fornara
  • METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180158530
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180145040
    Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180145039
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT WITHOUT ADDITION OF ADDITIONAL MATERIAL, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20180145027
    Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 24, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Guilhem Bouton, Mathieu Lisart
  • EEPROM CELL WITH CHARGE LOSS
    Publication number: 20180136611
    Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventor: Pascal Fornara
  • INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES
    Publication number: 20180130881
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 10, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • INTEGRATED CIRCUIT COMPRISING AN ANTIFUSE STRUCTURE AND METHOD OF REALIZING
    Publication number: 20180130740
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Application
    Filed: May 31, 2017
    Publication date: May 10, 2018
    Inventors: Pascal Fornara, Christian Rivero
  • Zener diode having an adjustable breakdown voltage
    Patent number: 9954119
    Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Roberto Simola, Pascal Fornara
  • METHOD FOR GENERATION OF ELECTRICAL POWER WITHIN A THREE-DIMENSIONAL INTEGRATED STRUCTURE AND CORRESPONDING LINK DEVICE
    Publication number: 20180090541
    Abstract: Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically intercoupled by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically coupled in series and thermally coupled in parallel and contained within the said region subjected to the said temperature gradient.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 29, 2018
    Inventors: Christian Rivero, Pascal Fornara
  • Method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face and corresponding integrated circuit
    Patent number: 9916902
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: March 13, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 9899476
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT
    Publication number: 20180025990
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales