Patents by Inventor Patrice Besse
Patrice Besse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160276335Abstract: An ESD protection device comprising an SCR -type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area of an N-type well. One or more diodes connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers between doped regions instead of gate oxide technology significantly reduces unwanted leakage currents.Type: ApplicationFiled: October 18, 2013Publication date: September 22, 2016Inventors: Jean Philippe LAINE, Patrice BESSE
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Publication number: 20160276460Abstract: An ESD protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the ESD protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type. Wherein no contact region is formed within a surface of the semiconductor structure of the second doping type between the first and second semiconductor regions of the first doping type.Type: ApplicationFiled: August 19, 2015Publication date: September 22, 2016Inventors: Jean Philippe LAINE, Patrice BESSE
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Publication number: 20160276332Abstract: An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.Type: ApplicationFiled: August 19, 2015Publication date: September 22, 2016Inventors: Jean Philippe LAINE, Patrice BESSE
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Electrostatic discharge protection circuit arrangement, electronic circuit and ESD protection method
Patent number: 9438031Abstract: An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold.Type: GrantFiled: February 29, 2012Date of Patent: September 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Jerome Casters, Jean-Philippe Laine, Alain Salles -
Patent number: 9413160Abstract: A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back MOS switch. The circuit receives an input driving signal and provides a driving output signal to common gates of the p-type back-to-back MOS switch. The circuit comprises a driving signal insulation switch for disconnecting the common gate of the p-type back-to-back MOS switch from the received input driving signal when the voltage of the common gates is larger than the supply voltage of the circuit. The circuit further comprises a gate source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate if a received voltage at the common sources is larger than a reference voltage Vref.Type: GrantFiled: April 19, 2012Date of Patent: August 9, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Yuan Gao, Patrice Besse, Thierry Laplagne
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Publication number: 20160156180Abstract: An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. The output of the silicon controlled rectifier constitutes a first output of the respective unit and is connected to an input terminal of the circuit. The output of the current mirror constitutes a second output of the respective unit and is connected with the reference input terminal of the circuit. Thus the units are connected in series but the output terminals of the current mirrors are all connected with the reference input terminal, which may be a ground terminal, so as to minimise the breakdown resistance of the circuit.Type: ApplicationFiled: May 4, 2015Publication date: June 2, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: PATRICE BESSE, PHILIPPE GIVELIN, JEAN PHILIPPE LAINE
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Patent number: 9318448Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.Type: GrantFiled: May 30, 2012Date of Patent: April 19, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice Besse, Kamel Abouda, Valerie Bernon-Enjalbert, Philippe Givelin
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Publication number: 20160061891Abstract: A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit 100 comprises in addition to a clock network 110 an integrated test clock signal generator 140 to generate test clock signals that are provided via controllable multiplexers 150, 160 to an analogue and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. The test clock signals are generated on basis of an input test clock signal having a controllable frequency. The clock network generates clock signals for the sub-circuitries that are used by the sub-circuitries under normal operational conditions. The controllable multiplexers provide either the test clock signal to a specific sub-circuitry or a clock signal received from the clock network.Type: ApplicationFiled: January 28, 2015Publication date: March 3, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: PASCAL KAMEL ABOUDA, CELINE HOUNAÏDA ABOUDA, PATRICE BESSE
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Patent number: 9224726Abstract: An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off.Type: GrantFiled: June 4, 2008Date of Patent: December 29, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Matthijs Pardoen, Patrice Besse
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Publication number: 20150369845Abstract: An integrated circuit die includes a stack of a substrate and multiple layers extending in parallel to the substrate. A number of integrated electronic components is formed in the stack, and connected to form an electronic circuit. The electronic circuit comprises a first electric contact, a second electric contact, and a coupling which couples the electric strips electrically to each other. The coupling includes a circuit via which extends through at least two of the layers. The die further includes an integrated current sensor having a coil arrangement for sensing a current flowing through a part of the electronic circuit. The coil arrangement is magnetically coupled to the circuit via over at least a part of a length of the circuit via to sensing a magnetic flux through the circuit via. A measurement unit can measure a parameter of the coil arrangement representative of a current flowing through the circuit via.Type: ApplicationFiled: February 15, 2013Publication date: December 24, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ALAIN SALLES, KAMEL ABOUDA, PATRICE BESSE
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Publication number: 20150311193Abstract: A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.Type: ApplicationFiled: August 22, 2012Publication date: October 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Jean Philippe LAINE, Patrice BESSE
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Publication number: 20150276847Abstract: A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time.Type: ApplicationFiled: October 10, 2012Publication date: October 1, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Alain SALLES, Patrice BESSE, Stéphane COMPAING, Philippe DEBOSQUE
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Publication number: 20150276815Abstract: A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device.Type: ApplicationFiled: November 6, 2012Publication date: October 1, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Alain SALLES, Kamel ABOUDA, Patrice BESSE
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Publication number: 20150221633Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.Type: ApplicationFiled: August 3, 2012Publication date: August 6, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jean Philippe Laine, Patrice Besse
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Publication number: 20150221629Abstract: A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad.Type: ApplicationFiled: September 12, 2012Publication date: August 6, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Alexis Huot-Marchand, Jean-Philippe Laine, Alain Salles
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Patent number: 9099306Abstract: An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.Type: GrantFiled: January 20, 2012Date of Patent: August 4, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Philippe Givelin, Eric Rolland
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Patent number: 9077171Abstract: A reference voltage loss monitoring circuit having a first and second reference node. The reference nodes are connected to a voltage reference. A first connection device is connects the first reference node to the second reference node, and includes a first diode to allow a current flowing from the first reference node to the reference ground node and not conversely. The first diode includes a first main transistor. A second connection device connects the second reference node to the first reference node, and includes a second diode to allow a current flowing from the second reference node to first reference node and not conversely. The second diode includes a second main transistor. Each of the first and second connection devices further includes a secondary transistor mirrored with the main transistor of the connection devices.Type: GrantFiled: May 27, 2011Date of Patent: July 7, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Philippe Givelin, Patrice Besse, Estelle Huynh
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Publication number: 20150129928Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.Type: ApplicationFiled: May 30, 2012Publication date: May 14, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice Besse, Kamel Abouda, Valerie Bernon-Enjalbert, Philippe Givelin
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Publication number: 20150098160Abstract: A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back MOS switch. The circuit receives an input driving signal and provides a driving output signal to common gates of the p-type back-to-back MOS switch. The circuit comprises a driving signal insulation switch for disconnecting the common gate of the p-type back-to-back MOS switch from the received input driving signal when the voltage of the common gates is larger than the supply voltage of the circuit. The circuit further comprises a gate source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate if a received voltage at the common sources is larger than a reference voltage Vref.Type: ApplicationFiled: April 19, 2012Publication date: April 9, 2015Applicant: Freescale Semiconductor, Inc,Inventors: Yuan Gao, Patrice Besse, Thierry Laplagne
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Publication number: 20150076556Abstract: An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.Type: ApplicationFiled: January 20, 2012Publication date: March 19, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Patrice Besse, Philippe Givelin, Eric Rolland