Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.

Abstract: Systems, apparatus, and methods are disclosed for foreline diagnostics and control. A foreline coupled to a chamber exhaust is instrumented with one or more sensors, in some embodiments placed between the chamber exhaust and an abatement system. The one or more sensors are positioned to measure pressure in the foreline as an indicator of conductance. The sensors are coupled to a trained machine learning model configured to provide a signal when the foreline needs a cleaning cycle or when preventive maintenance should be performed. In some embodiments, the trained machine learning predicts when cleaning or preventive maintenance will be needed.

Abstract: Aspects generally relate to methods, systems, and apparatus for conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system. In one aspect, a corrected flow curve is created for a range of target flow rates across a plurality of setpoints. In one implementation, a method of conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system includes prioritizing the plurality of MFCs for the calibration operation. The prioritizing includes determining an operation time for each MFC of the plurality of MFCs, and ranking the plurality of MFCs in a rank list according to the operation time for each MFC. The method includes conducting the calibration operation for the plurality of MFCs according to the rank list and during an idle time for the substrate processing system.

Abstract: Aspects generally relate to methods, systems, and apparatus for conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system. In one aspect, a corrected flow curve is created for a range of target flow rates across a plurality of setpoints. In one implementation, a method of conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system includes prioritizing the plurality of MFCs for the calibration operation. The prioritizing includes determining an operation time for each MFC of the plurality of MFCs, and ranking the plurality of MFCs in a rank list according to the operation time for each MFC. The method includes conducting the calibration operation for the plurality of MFCs according to the rank list and during an idle time for the substrate processing system.

Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Abstract: A method and apparatus for forming a super-lattice structure on a substrate is described herein. The super-lattice structure includes a plurality of silicon-germanium layers and a plurality of silicon layers disposed in a stacked pattern. The methods described herein produce a super-lattice structure with transition width of less than about 1.4 nm between each of the silicon-germanium layers and an adjacent silicon layer. The methods described herein include flowing one or a combination of a silicon containing gas, a germanium containing gas, and a halogenated species.

Abstract: Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

Abstract: Aspects generally relate to methods, systems, and apparatus for conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system. In one aspect, a corrected flow curve is created for a range of target flow rates across a plurality of setpoints. In one implementation, a method of conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system includes prioritizing the plurality of MFCs for the calibration operation. The prioritizing includes determining an operation time for each MFC of the plurality of MFCs, and ranking the plurality of MFCs in a rank list according to the operation time for each MFC. The method includes conducting the calibration operation for the plurality of MFCs according to the rank list and during an idle time for the substrate processing system.

Abstract: Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

Abstract: Embodiments of the present disclosure generally relate to an apparatus and method of processing a substrate. In at least one embodiment, an apparatus includes a chamber body, a substrate support assembly and a bracket assembly disposed outside the chamber body and coupled to the substrate support assembly. The bracket assembly has a plurality of leveling screws for adjusting a level of the substrate support assembly. The apparatus includes an actuator coupled to one of the plurality of leveling screws and an accelerometer coupled to the substrate support assembly. The accelerometer is configured to indicate an orientation of the substrate support assembly. The apparatus includes a control module in communication with the actuator and the accelerometer. The control module is configured to determine the level of the substrate support assembly based on the orientation indicated by the accelerometer and adjust the level of the substrate support assembly using the actuator.

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Abstract: One or more embodiments herein relate to methods for detection using optical emission spectroscopy. In these embodiments, an optical signal is delivered from the process chamber to an optical emission spectrometer (OES). The OES identifies emission peaks of photons, which corresponds to the optical intensity of radiation from the photons, to determine the concentrations of each of the precursor gases and reaction products. The OES sends input signals of the data results to a controller. The controller can adjust process variables within the process chamber in real time during deposition based on the comparison. In other embodiments, the controller can automatically trigger a process chamber clean based on a comparison of input signals of process chamber residues received before the deposition process and input signals of process chamber residues received after the deposition process.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: An apparatus for controlling temperature profile of a substrate within an epitaxial chamber includes a bottom center pyrometer and a bottom outer pyrometer to respectively measure temperatures at a center location and an outer location of a first surface of a susceptor of an epitaxy chamber, a top center pyrometer and a top outer pyrometer to respectively measure temperatures at a center location and an outer location of a substrate disposed on a second surface of the susceptor opposite the first surface, a first controller to receive signals, from the bottom center pyrometer and the bottom outer pyrometer, and output a feedback signal to a first heating lamp module that heats the first surface based on the measured temperatures of the first surface, and a second controller to receive signals, from the top center pyrometer, the top outer pyrometer, the bottom center pyrometer, and the bottom outer pyrometer, and output a feedback signal to a second heating lamp module that heats the substrate based on the mea

Abstract: Systems, apparatus, and methods are disclosed for foreline diagnostics and control. A foreline coupled to a chamber exhaust is instrumented with one or more sensors, in some embodiments placed between the chamber exhaust and an abatement system. The one or more sensors are positioned to measure pressure in the foreline as an indicator of conductance. The sensors are coupled to a trained machine learning model configured to provide a signal when the foreline needs a cleaning cycle or when preventive maintenance should be performed. In some embodiments, the trained machine learning predicts when cleaning or preventive maintenance will be needed.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: The present invention provides methods and apparatus for processing semiconductor substrates in an epitaxy chamber configured to map a temperature profile for both substrates and interior chamber components. In one embodiment, the semiconductor processing chamber has a body having ceiling and a lower portion defining an interior volume. A substrate support is disposed in the interior volume. A mounting plate is coupled to the ceiling outside the interior volume. A movement assembly is coupled to the mounting plate. A sensor is coupled to the movement assembly and moveable relative to the ceiling. The sensor is configured to detect a temperature location in the interior volume.

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

Abstract: The present invention provides methods and apparatus for processing semiconductor substrates in an epitaxy chamber configured to map a temperature profile for both substrates and interior chamber components. In one embodiment, the semiconductor processing chamber has a body having ceiling and a lower portion defining an interior volume. A substrate support is disposed in the interior volume. A mounting plate is coupled to the ceiling outside the interior volume. A movement assembly is coupled to the mounting plate. A sensor is coupled to the movement assembly and moveable relative to the ceiling. The sensor is configured to detect a temperature location in the interior volume.