Patents by Inventor Patricia M. Liu

Patricia M. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872763
    Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include delivering a nitrogen-containing precursor or an oxygen-containing precursor to a substrate contained in a semiconductor processing chamber. The methods may include forming reactive ligands on an exposed surface of the substrate with the nitrogen-containing precursor or the oxygen-containing precursor. The methods may also include forming a high-k dielectric material overlying the substrate.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 22, 2020
    Assignee: Applied Materials, Inc.
    Inventors: David Chu, Steven C. Hung, Malcolm J. Bevan, Charles Chu, Tatsuya E. Sato, Shih-Chung Chen, Patricia M. Liu, Johanes Swenberg
  • Patent number: 10861722
    Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 8, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Benjamin Colombeau, Sheng-Chin Kung, Patricia M. Liu
  • Publication number: 20200350157
    Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include delivering a nitrogen-containing precursor or an oxygen-containing precursor to a substrate contained in a semiconductor processing chamber. The methods may include forming reactive ligands on an exposed surface of the substrate with the nitrogen-containing precursor or the oxygen-containing precursor. The methods may also include forming a high-k dielectric material overlying the substrate.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 5, 2020
    Applicant: Applied Materials, Inc.
    Inventors: David Chu, Steven C. Hung, Malcolm J. Bevan, Charles Chu, Tatsuya E. Sato, Shih-Chung Chen, Patricia M. Liu, Johanes Swenberg
  • Publication number: 20200258997
    Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.
    Type: Application
    Filed: January 27, 2020
    Publication date: August 13, 2020
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
  • Publication number: 20200203490
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Application
    Filed: November 8, 2019
    Publication date: June 25, 2020
    Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
  • Publication number: 20200152493
    Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 14, 2020
    Inventors: Benjamin COLOMBEAU, Sheng-Chin KUNG, Patricia M. LIU
  • Publication number: 20200091010
    Abstract: The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 19, 2020
    Inventors: Xuebin LI, Schubert S. CHU, Errol Antonio C. SANCHEZ, Patricia M. LIU, Gaurav THAREJA, Raymond HUNG
  • Publication number: 20200013625
    Abstract: Methods for depositing a metal silicide are provide and include heating a substrate having a silicon-containing surface to a deposition temperature, and exposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process. The deposition gas contains a silicon precursor, a titanium or other metal precursor, and a phosphorus or other non-metal precursor.
    Type: Application
    Filed: May 20, 2019
    Publication date: January 9, 2020
    Inventors: Xuebin LI, Patricia M. LIU
  • Publication number: 20200013624
    Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.
    Type: Application
    Filed: May 1, 2019
    Publication date: January 9, 2020
    Inventors: Xuebin LI, Errol Antonio C. SANCHEZ, Patricia M. LIU
  • Publication number: 20200013878
    Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 9, 2020
    Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
  • Patent number: 9437640
    Abstract: Backside illuminated sensors and methods of manufacture are described. Specifically, a backside illuminated sensor with a dipole modulating layer near the photodiode is described.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 6, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Sherry Mings, Patricia M. Liu, Steven C. H. Hung
  • Publication number: 20160215392
    Abstract: Apparatus and methods for spatial atomic layer deposition are disclosed. The apparatus include a gas delivery system comprising a first gas flowing through a plurality of legs in fluid communication with a valve and a second gas flowing through a plurality of legs into the valves.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 28, 2016
    Inventors: Joseph Yudovsky, Kevin Griffin, Aaron Miller, Jeff Tobin, Eran Newman, Tatsuya E. Sato, Patricia M. Liu
  • Patent number: 9048183
    Abstract: Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: June 2, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Seshadri Ganguli, Srinivas Gandikota, Yu Lei, Xinliang Lu, Sang Ho Yu, Hoon Kim, Paul F. Ma, Mei Chang, Maitreyee Mahajani, Patricia M. Liu
  • Publication number: 20150069476
    Abstract: Backside illuminated sensors and methods of manufacture are described. Specifically, a backside illuminated sensor with a dipole modulating layer near the photodiode is described.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 12, 2015
    Inventors: Sherry Mings, Patricia M. Liu, Steven C.H. Hung
  • Patent number: 8778816
    Abstract: Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water below the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 15, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya E. Sato, David Thompson, Jeffrey W. Anthis, Vladimir Zubkov, Steven Verhaverbeke, Roman Gouk, Maitreyee Mahajani, Patricia M. Liu, Malcolm J. Bevan
  • Publication number: 20140120712
    Abstract: Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5.
    Type: Application
    Filed: January 3, 2014
    Publication date: May 1, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Seshadri GANGULI, Srinivas GANDIKOTA, Yu LEI, Xinliang LU, Sang Ho YU, Hoon KIM, Paul F. MA, Mei CHANG, Maitreyee MAHAJANI, Patricia M. LIU
  • Patent number: 8658522
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Patent number: 8642468
    Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Srinivas Gandikota, Yu Lei, Xinliang Lu, Sang Ho Yu, Hoon Kim, Paul F. Ma, Mei Chang, Maitreyee Mahajani, Patricia M. Liu
  • Patent number: 8375892
    Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: February 19, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Tatsuya Sato, Patricia M. Liu, Fanos Christodoulou
  • Publication number: 20120220116
    Abstract: A deposition process including a dry etch process, followed by a deposition process of a high-k dielectric is disclosed. The dry etch process involves placing a substrate to be cleaned into a processing chamber to remove surface oxides. A gas mixture is energized to form a plasma of reactive gas which reacts with an oxide on the substrate, forming a thin film. The substrate is heated to vaporize the thin film and expose a substrate surface. The substrate surface is substantially free of oxides. Deposition is then used to form a layer on the substrate surface.
    Type: Application
    Filed: July 27, 2011
    Publication date: August 30, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Atif Noori, Maitreyee Mahajani, Patricia M. Liu, Steven Hung, Tatsuya E. Sato, Mei Chang