Patents by Inventor Patricia M. Liu
Patricia M. Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220033970Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.Type: ApplicationFiled: June 30, 2021Publication date: February 3, 2022Inventors: Xuebi LI, Errol Antonio C. SANCHEZ, Patricia M. LIU
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Publication number: 20220005704Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.Type: ApplicationFiled: September 17, 2021Publication date: January 6, 2022Inventors: Xuebin LI, Wei LIU, Gaurav THAREJA, Shashank SHARMA, Patricia M. LIU, Schubert CHU
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Publication number: 20220005705Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.Type: ApplicationFiled: September 17, 2021Publication date: January 6, 2022Inventors: Xuebin LI, Wei LIU, Gaurav THAREJA, Shashank SHARMA, Patricia M. LIU, Schubert CHU
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Publication number: 20210398814Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.Type: ApplicationFiled: June 15, 2021Publication date: December 23, 2021Applicant: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes F. Swenberg
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Patent number: 11195914Abstract: Embodiments of the present disclosure relate to a transistor and methods for forming a transistor. A transistor includes a gate electrode structure disposed over a channel region, a source/drain extension region disposed adjacent to the channel region, and a source/drain region disposed on the source/drain extension region. The source/drain region includes antimony (Sb). The method of forming a transistor includes forming the source/drain extension region and forming the source/drain region on the source/drain extension region. The antimony helps prevent unwanted migration of dopants from the source/drain region to the source/drain extension region.Type: GrantFiled: September 30, 2019Date of Patent: December 7, 2021Assignee: Applied Materials, Inc.Inventors: Patricia M. Liu, Flora Fong-Song Chang, Zhiyuan Ye
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Patent number: 11195923Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.Type: GrantFiled: November 8, 2019Date of Patent: December 7, 2021Assignee: Applied Materials, Inc.Inventors: Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Vidyadhar Mandrekar, Andy Lo, Patricia M. Liu, Sanjay Natarajan, Saurabh Chopra
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Patent number: 11152221Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.Type: GrantFiled: February 7, 2020Date of Patent: October 19, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Xuebin Li, Wei Liu, Gaurav Thareja, Shashank Sharma, Patricia M. Liu, Schubert Chu
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Patent number: 11152479Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.Type: GrantFiled: January 27, 2020Date of Patent: October 19, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Andy Lo, Patricia M. Liu, Sanjay Natarajan, Saurabh Chopra
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Patent number: 11081358Abstract: Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.Type: GrantFiled: May 1, 2019Date of Patent: August 3, 2021Assignee: Applied Materials, Inc.Inventors: Xuebin Li, Errol Antonio C. Sanchez, Patricia M. Liu
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Patent number: 11037838Abstract: The systems and methods discussed herein are for a cluster tool that can be used for MOSFET device fabrication, including NMOS and PMOS devices. The cluster tool includes process chambers for pre-cleaning, metal-silicide or metal-germanide film formation, and surface protection operations such as capping and nitridation. The cluster tool can include one or more process chambers configured to form a source and a drain. The devices fabricated in the cluster tool are fabricated to have at least one protective layer formed over the metal-silicide or metal-germanide film to protect the film from contamination during handling and transfer to separate systems.Type: GrantFiled: September 3, 2019Date of Patent: June 15, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Xuebin Li, Schubert S. Chu, Errol Antonio C. Sanchez, Patricia M. Liu, Gaurav Thareja, Raymond Hoiman Hung
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Publication number: 20210134986Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.Type: ApplicationFiled: October 26, 2020Publication date: May 6, 2021Applicant: Applied Materials, Inc.Inventors: Steven C. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes Swenberg
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Patent number: 10971366Abstract: Methods for depositing a metal silicide are provide and include heating a substrate having a silicon-containing surface to a deposition temperature, and exposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process. The deposition gas contains a silicon precursor, a titanium or other metal precursor, and a phosphorus or other non-metal precursor.Type: GrantFiled: May 20, 2019Date of Patent: April 6, 2021Assignee: Applied Materials, Inc.Inventors: Xuebin Li, Patricia M. Liu
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Publication number: 20210028280Abstract: Embodiments of the present disclosure relate to a transistor and methods for forming a transistor. A transistor includes a gate electrode structure disposed over a channel region, a source/drain extension region disposed adjacent to the channel region, and a source/drain region disposed on the source/drain extension region. The source/drain region includes antimony (Sb). The method of forming a transistor includes forming the source/drain extension region and forming the source/drain region on the source/drain extension region. The antimony helps prevent unwanted migration of dopants from the source/drain region to the source/drain extension region.Type: ApplicationFiled: September 30, 2019Publication date: January 28, 2021Inventors: Patricia M. LIU, Flora Fong-Song CHANG, Zhiyuan YE
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Publication number: 20210028075Abstract: A method for processing a substrate within a processing chamber comprises receiving a first radiation signal corresponding to a film on a target element disposed within the processing chamber, analyzing the first radiation signal, and controlling the processing of the substrate based on the analyzed first radiation signal. The processing chamber includes a substrate support configured to support the substrate within a processing volume and a controller coupled to a first sensing device configured to receive the first radiation signal.Type: ApplicationFiled: July 24, 2020Publication date: January 28, 2021Inventors: Zuoming ZHU, Shu-Kwan LAU, Ala MORADIAN, Enle CHOO, Flora Fong-Song CHANG, Vilen K. NESTOROV, Zhiyuan YE, Bindusagar MARATH SANKARATHODI, Maxim D. SHAPOSHNIKOV, Surendra Singh SRIVASTAVA, Zhepeng CONG, Patricia M. LIU, Errol C. SANCHEZ, Jenny C. LIN, Schubert S. CHU, Balakrishnam R. JAMPANA
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Patent number: 10872763Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include delivering a nitrogen-containing precursor or an oxygen-containing precursor to a substrate contained in a semiconductor processing chamber. The methods may include forming reactive ligands on an exposed surface of the substrate with the nitrogen-containing precursor or the oxygen-containing precursor. The methods may also include forming a high-k dielectric material overlying the substrate.Type: GrantFiled: May 3, 2019Date of Patent: December 22, 2020Assignee: Applied Materials, Inc.Inventors: David Chu, Steven C. Hung, Malcolm J. Bevan, Charles Chu, Tatsuya E. Sato, Shih-Chung Chen, Patricia M. Liu, Johanes Swenberg
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Patent number: 10861722Abstract: Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.Type: GrantFiled: September 23, 2019Date of Patent: December 8, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Benjamin Colombeau, Sheng-Chin Kung, Patricia M. Liu
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Publication number: 20200350157Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include delivering a nitrogen-containing precursor or an oxygen-containing precursor to a substrate contained in a semiconductor processing chamber. The methods may include forming reactive ligands on an exposed surface of the substrate with the nitrogen-containing precursor or the oxygen-containing precursor. The methods may also include forming a high-k dielectric material overlying the substrate.Type: ApplicationFiled: May 3, 2019Publication date: November 5, 2020Applicant: Applied Materials, Inc.Inventors: David Chu, Steven C. Hung, Malcolm J. Bevan, Charles Chu, Tatsuya E. Sato, Shih-Chung Chen, Patricia M. Liu, Johanes Swenberg
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Publication number: 20200266068Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.Type: ApplicationFiled: February 7, 2020Publication date: August 20, 2020Inventors: Xuebin LI, Wei LIU, Gaurav THAREJA, Shashank SHARMA, Patricia M. LIU, Schubert CHU
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Publication number: 20200258997Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.Type: ApplicationFiled: January 27, 2020Publication date: August 13, 2020Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
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Publication number: 20200203490Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.Type: ApplicationFiled: November 8, 2019Publication date: June 25, 2020Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA