Abstract: A method for switching frames in a switching system is provided. The method includes receiving a first stripe set for a first port at a second port. The first stripe set is stored in a particular location in a queue of the second port. A determination is made regarding whether a first full flag associated with the first port has been set. If the first full flag has not been set, the first full flag is set and the particular location in the queue of the second port is provided to the first port.

Abstract: Data compression in a communication system is achieved by performing an error correction encoding operation on input data, and then providing, for transmission across a communication channel, compressed data that is representative of the input data and includes error correction information produced by the error correction encoding operation.

Abstract: A method for processing frames in a switching system is provided. The method includes performing a data striping technique on an incoming high data rate (HDR) data stream having a high data rate to generate a plurality of lower data rate (LDR) stripes having a lower data rate than the high data rate. The plurality of LDR stripes is processed using processing techniques associated with the lower data rate. The processed LDR stripes are multiplexed into a single, outgoing HDR data stream.

Abstract: A routing apparatus comprising: 1) a first router coupled to a first plurality of Ethernet links; and 2) a second router coupled to a second plurality of Ethernet links, wherein selected ones of the first plurality of Ethernet links are coupled to selected ones of the second plurality of Ethernet links to thereby form Ethernet trunk groups in which traffic associated with a plurality of Ethernet ports are aggregated into a single logical port. The routing apparatus further comprises a first high-speed link and a second high-speed link directly coupling the first router and the second router and forming a self-healing ring for transferring data packets between the first and second routers. In response to a failure associated with the failing one of the first and second routers, the first and second high-speed links transfer data traffic from the failing router to the non-failing router.

Abstract: A router for transferring data packets between external devices. The router comprises: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor comprising a first plurality of microengines capable of forwarding incoming data packets from external ports to the switch fabric; ii) an outbound network processor comprising a second plurality of microengines capable of forwarding outgoing data packets from the switch fabric to the external ports; and iii) an asynchronous variables circuit for controlling access of the inbound and outbound network processors to at least one of i) a shared resource and ii) a shared variable in the router.

Abstract: A router for transferring data packets between external devices. The router comprises: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor having a first plurality of microengines that forward incoming data packets from external ports to the switch fabric; ii) an outbound network processor having a second plurality of microengines that forward outgoing data packets from the switch fabric to the external ports; and iii) a plurality of registers for transferring messages between the first and second plurality of microengines. The registers may be 32-bit mailboxes for transferring short messages or 2 Kbyte FIFO buffers for transferring one or more large data packets.

Abstract: An accelerated operating system can increase the data processing throughput of a data processor executing an application according to a sequential programming model. An application running on a main data processor is interfaced to an operating system which has been accelerated by distributing at least some of the operating system among a plurality of subordinate data processors which provide data processing support for the application running on the main data processor. The subordinate data processors can thus also provide operating system support for the application running on the main data processor. This decreases the processing burden on the main data processor, thereby increasing the main data processor's data processing throughput while executing the application.

Abstract: A router for interconnecting external devices comprising: 1) a switch fabric; and 2) R routing nodes coupled to the switch fabric. Each of the R routing nodes exchanges data packets with the external devices via network interface ports and with other routing nodes via the switch fabric. A first routing node comprises: i) an inbound network processor for receiving incoming data packets from a network interface port; ii) an outbound network processor for transmitting data packets to the network interface port; and iii) a shared memory accessible by the inbound and outbound network processors for storing a current trie tree search table and a current vector table used to index into the trie tree search table. A control plane processor generates an updated vector table to replace the current vector table and notifies the inbound and outbound network processors that the updated vector table is available.

Abstract: Channelized I/O is provided for a data processing architecture. An application is executed on a data processor. Program instructions are executed in parallel, and independently of the data processor, to provide a plurality of data communication channels which can communicate with an external site that is physically separate from the data processor.

Abstract: A packet counter/adder for use in a multiprocessor system. The packet counter stores a counter value of data packets processed by a plurality of processors in the multiprocessor system. The packet counter comprises a first register capable of storing the counter value, wherein the counter value in the first register is incremented by a write operation to a first address associated with the first register. The counter value in the first register may be set to a specified value by a write operation to a second address associated with the first register.

Abstract: A router for interconnecting external devices. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and for transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric and control data processing circuitry capable of performing control and management functions. The control data processing circuitry comprises a first network processor for performing control and management functions associated with the router and a second network processor for performing control and management functions associated with the router. The control and management functions are dynamically allocated between the first network processor and the second network processor.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises: 1) a switch fabric; and 2) a plurality of routing nodes coupled to the switch fabric, wherein each of the plurality of routing nodes comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and for transmitting data packets to, and receiving data packets from, other ones of the plurality of routing nodes via the switch fabric. The packet processing circuitry comprises: i) a first network processor comprising a first plurality of microengines, each of the first plurality of microengines capable of performing security and classification functions associated with the data packets; and ii) a second network processor comprising a second plurality of microengines, each of the second plurality of microengines capable of performing security and classification functions associated with the data packets.

Abstract: A router comprising a switch fabric and routing nodes coupled to the switch fabric. Each routing node comprises a trie tree search table for storing routing information associated with received variable length subnet masks. The trie tree search table comprises a plurality of stages that are searched by N-bit address symbols derived from the received variable length subnet masks. Each routing node also comprises a control processor for generating the stages associated with the trie tree search table. The control processor generates for each entry in a first one of the plurality of stages: 1) an end flag indicating whether each entry is a leaf or a branch; 2) a subnet flag indicating whether a subnet mask ends at each entry; and 3) a masked flag indicating whether a subnet mask ending at each entry ends on a boundary of an N-bit address symbol associated with entry.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises: i) a switch fabric; ii) a plurality of routing nodes coupled to the switch fabric, wherein each of the plurality of routing nodes is capable of exchanging data packets with the external devices and with other ones of the plurality of routing nodes via the switch fabric; and iii) a first control processor associated with a first one of the plurality of routing nodes capable of generating a first refined redistribution metric associated with a first route in a routing table of the first routing node. The first control processor generates the first refined redistribution metric based on 1) a first default redistribution metric associated with a first routing protocol associated with the first route and 2) a first routing protocol metric received from the first routing protocol associated with the first route.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node comprises packet processing circuitry for transmitting data packets to, and receiving data packets from, the external devices and transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The packet processing circuitry comprises a first network processor comprising: i) N microengines for forwarding the data packets, each of the microengines capable of executing a plurality of threads that perform forwarding table lookup operations; and ii) workload distribution circuitry for distributing data packets to the N microengines for forwarding.

Abstract: A routing table search circuit for determining a first destination address for a first received data packet. The routing table search circuit comprises: i) a forwarding table containing destination addresses; and ii) a trie tree search table for translating an address portion of the first received data packet into a destination pointer for accessing the first destination address in the forwarding table. A first stage of the trie tree search table is searched using a received address pointer from a previous stage of the trie tree search table and a first m-bit symbol of the address portion. The routing table search circuit also comprises at least one consecutive symbols table and a control circuit for determining that a second consecutive m-bit symbol is the same as the first m-bit symbol. The control circuit then determines a total number of consecutive identical m-bit symbols beginning with the first m-bit symbol.

Abstract: A routing table search circuit comprising a forwarding table containing forwarding table entries, each forwarding table entry comprising a destination address, and a content addressable memory (CAM) comprising a CAM lookup table, the CAM receiving a search key and outputting a CAM search result corresponding to the search key from the CAM lookup table. The search key comprises at least: i) a packet type field associated with the first received address and ii) an address field containing a most significant bits portion of the first received address. The routing table search circuit also comprises M pipelined memory stages for storing a trie table that translates the first received address into the first destination address. The M pipelined memory stages are searched using the CAM search result and a remaining bits portion of the first received address. Each of the M pipelined memory stages outputs a stage search result.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each of the routing nodes transmits data packets to, and receives data packets from, the external devices and other routing nodes via the switch fabric. The switch fabric detects that the output bandwidth of a first output of the switch fabric has been exceeded and, in response to the detection, attempts to slow the input ports and drops lower priority packets if necessary. The routing nodes give precedence to routing higher priority packets.

Abstract: A base station for use in a point-to-multipoint wireless network. The base station transmits downstream data packets in a downstream traffic channel to customer premises equipment (CPE) devices and receives upstream data packets in an upstream traffic channel from the CPE devices. The base station determines queue status of at least one queue associated with at least one application in each of the CPE devices and, in response to the determination, the base station re-allocates bandwidth from a first queue associated with a first CPE device to a second queue.

Abstract: A router comprising: i) a switch fabric; and ii) N Layer 2 modules coupled by the switch fabric, each of the N Layer 2 modules capable of receiving data packets in Layer 2 frames and forwarding the received data packets using Layer 2 addresses associated with the Layer 2 frames, wherein a first one of the Layer 2 modules comprises a Layer 3 routing engine capable of forwarding a first received data packet through the switch fabric directly to a second one of the Layer 2 modules using a Layer 3 address associated with the first received data packet if the first Layer 2 module does not recognize a Layer 2 address associated with the first received data packet.