Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each of the routing nodes exchanges data packets with the external devices via network interface ports and with other routing nodes via the switch fabric. A first routing node comprises an inbound network processor capable of receiving incoming data packets from a network interface port; an outbound network processor capable of transmitting data packets to the network interface port; and a shared memory for storing forwarding table information used by the inbound and outbound network processors. The shared memory comprises an inbound upper bank capable of storing forwarding table information accessed by the inbound network processor and an inbound lower bank capable of storing forwarding table information accessed by the inbound network processor.

Abstract: A router for interconnecting N interfacing peripheral devices. The router comprises routing nodes coupled to one another via switching circuitry. A first routing nodes comprises: 1) a physical medium device (PMD) module for transmitting data packets to and receiving data packets from the N interfacing peripheral devices; 2) an ingress processor for receiving incoming data packets from the PMD module; 3) an egress processor for transmitting data packets to the PMD module; and 4) a medium access control (MAC) processor for forwarding data packets from the ingress processor to the switching circuitry and forwarding data packets from the switching circuitry to the egress processor. The MAC processor determines whether a first data packet received from the ingress processor is directed to the egress processor and, if so, transfers the first data packet directly to the egress processor without forwarding the first data packet through the switching circuitry.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A routing node determines packet lengths of data packets received in the routing node and sums packet lengths of data packets associated with particular routes. The routing node comprises a memory for storing route counters, wherein the route counters store counts of data packets for particular routes and store packet length sum values of data packets for particular routes. The routing node calculates a first bandwidth value from a first data packet count and a first packet length sum value stored in the route counters.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and routing nodes coupled to the switch fabric. Each routing node exchanges data packets with the external devices and with other routing nodes via the switch fabric. A first routing node identifies at least one traffic type indicia associated with data packets in the first routing node and counts data packets based on traffic type indicia. The first routing node comprises a memory for storing route counters and identification (ID) counters. The route counters store data packet counts for particular routes. The ID counters store data packet counts for particular traffic type indicia.

Abstract: A lookup circuit for translating received addresses into destination addresses. The lookup circuit comprises M pipelined memory circuits for storing a trie table for translating a first received address into a first destination address. The M memory circuits are pipelined such that a first portion of the first received address accesses an address table in a first memory circuit. An output of the first memory circuit comprises a first address pointer that indexes a start of an address table in a second memory circuit. The first address pointer and a second portion of the first received address access a particular entry in the address table in the second memory circuit. An output of the second memory circuit comprises a second address pointer that indexes a start of an address table in the third memory circuit, and so forth.

Abstract: A router for interconnecting N interfacing peripheral devices. The router comprises a switch fabric and routing nodes coupled to the switch fabric. Each routing node comprises: i) a plurality of physical medium device (PMD) modules for transmitting data packets to and receiving data packets from selected ones of the N interfacing peripheral devices; ii) an input-output processing (IOP) module coupled to the PMD modules and the switch fabric for routing the data packets between the PMD modules and the switch fabric and between the PMD modules; and iii) a classification module associated with the IOP module for classifying a first data packet received from the IOP module. The classification module causes the IOP module to forward the first data packet based on the classification. The router architecture incorporates streams-based billing support, firewall capabilities, and data surveillance functionality.

Abstract: A router for interconnecting N interfacing peripheral devices. The router comprises: i) a first switch fabric; ii) a second switch fabric; and iii) a plurality of routing nodes coupled to the first and second switch fabrics. Each of the routing nodes comprises an input-output processing (IOP) module for forwarding received data packets to other ones of the IOP modules via the first and second switch fabrics. A first one of the IOP modules forwards received data packets directed to a second one of the IOP modules by alternating between the first and second switch fabrics for each sequential data packet directed to the second IOP module. Breaks in the alternating sequence identify failed links and cause all traffic to be sent via the remaining good link. Support for multiple IOP modules and switch fabrics also is provided.

Abstract: A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node is capable of transmitting data packets to, and receiving data packets from, the external devices and is further capable of transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The router also comprises a control processor for comparing the N most significant bits of a first subnet address associated with a first external port of a first routing node with the N most significant bits of a second subnet address associated with a second external port of the first routing node. The router determines a P-bit prefix of similar leading bits in the first and second subnet addresses and transmits the P-bit prefix to other routing nodes.