Patents by Inventor Patrick B. Halahan

Patrick B. Halahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020115290
    Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods also provided.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 22, 2002
    Inventors: Patrick B. Halahan, Oleg Siniaguine
  • Publication number: 20020115260
    Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods also provided.
    Type: Application
    Filed: August 28, 2001
    Publication date: August 22, 2002
    Inventors: Patrick B. Halahan, Oleg Siniaguine
  • Publication number: 20020013061
    Abstract: A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then the wafer backside is etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and comers. The grooves' aspect ratio is large to reduce the lateral etch rate of the chip sidewalls and thus allow more area for on-chip circuitry.
    Type: Application
    Filed: June 6, 2001
    Publication date: January 31, 2002
    Inventors: Oleg Siniaguine, Patrick B. Halahan, Sergey Savastiouk
  • Patent number: 5442673
    Abstract: An x-ray collimator is described which is useful in an electron beam (EB) computed tomography (CT) scanner of the type in which a rotating electron beam is directed to impinge upon a ring-shaped target and the x-rays generated in response thereto are directed to a ring shaped detector array spaced therefrom. The collimator consists of an x-ray blocking septum having an aperture therein, the septum being located in a fixed position substantially co-planer with the planes of the target and the detector, so as to block all x-rays directed from said target to said detector except those which pass through said aperture. Tomographic slice width is determined by the "view" from the spot where the electron beam impinges upon the target, through the aperture, to the detector, and is variable by adjusting the position where the electron beam impinges upon the width of the x-ray target, and in a preferred embodiment, the position of a movable ring.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: August 15, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Roy E. Rand, Patrick B. Halahan