Patents by Inventor Patrick Carberry

Patrick Carberry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070241433
    Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.
    Type: Application
    Filed: April 19, 2007
    Publication date: October 18, 2007
    Inventors: Patrick Carberry, Jeffery Gilbert, George Libricz, Ralph Moyer, John Osenbach, Hugo Safar, Thomas Shilling
  • Publication number: 20060170079
    Abstract: An integrated circuit device is provided having a substrate, at least one integrated circuit element and a leadframe. The integrated circuit element and the leadframe are disposed on the substrate. The leadframe has at least one lead and at least one encapsulant dam disposed on the at least one lead. The encapsulant dam has at least one chamfered edge to provide clearance for a wire feed during a wire-bonding process.
    Type: Application
    Filed: February 2, 2005
    Publication date: August 3, 2006
    Inventors: John Brennan, Patrick Carberry, Joseph Freund, George Libricz, Ralph Moyer
  • Publication number: 20060172456
    Abstract: A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in the package, characterized by (c) causing energy from an external source to heat at least one predetermined segment of the wire to a temperature that is below its melting point (MP) but not below its recrystallization temperature (RCT), and (d) cooling the heated segment to a temperature below its RCT [e.g., to room temperature (RT)], thereby to increase the stiffness modulus of the segment. In one embodiment, the external source is a laser whose optical output is absorbed by the segment. In another embodiment, the heated segment is rapidly cooled (i.e., quenched) to RT.
    Type: Application
    Filed: November 5, 2003
    Publication date: August 3, 2006
    Inventors: Brett Campbell, Patrick Carberry, Jason Goodelle, Michael Quinn
  • Publication number: 20060145317
    Abstract: The specification describes a plastic cavity package for semiconductor devices that provides additional mechanical integrity for leads that extend from the plastic housing. Portions of the leads that are within the plastic housing are provided with cutouts. When the plastic housing is formed, or when the cavity is filled with polymer, plastic material fills the cutout, and joins to the mass of plastic on either side of the cutout, thus forming a continuous integral mass of plastic. The end result is that the plastic in the cutout, coupled to the main plastic mass, and to the rigid package sidewall, forms an effective anchor against pulling and bending forces the leads may encounter in manufacture or use.
    Type: Application
    Filed: December 31, 2004
    Publication date: July 6, 2006
    Inventors: John Brennan, Patrick Carberry, Jeffery Gilbert, George Libricz, Ralph Moyer, John Osenbach
  • Publication number: 20060131704
    Abstract: A semiconductor device package comprises a container having a base and side walls of an electrically insulating material. A semiconductor device chip is disposed on the base, and a lead frame extends through the side walls. At least one electrical conductor couples the lead frame to the chip. A first layer of an electrically insulating cured gel covers the chip and the lead frame, and a second layer of an electrically insulating cured gel covers at least the portion of the first layer that covers the chip, but does not extend to the side walls. In one embodiment, the second layer has the shape of a dome. In a preferred embodiment the gel comprises silicone. In another embodiment a third layer of conformal insulating material is disposed on the second layer and essentially fills the container. Also is described is a method of making the package for use with RFLDMOS chips.
    Type: Application
    Filed: December 18, 2004
    Publication date: June 22, 2006
    Inventors: Patrick Carberry, Jeffery Gilbert, George Libricz, Ralph Moyer
  • Publication number: 20060131707
    Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage-base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.
    Type: Application
    Filed: December 18, 2004
    Publication date: June 22, 2006
    Inventors: Patrick Carberry, Jeffery Gilbert, George Libricz, Ralph Moyer, John Osenbach, Hugo Safar, Thomas Shilling
  • Publication number: 20060001157
    Abstract: An integrated circuit comprises at least one circuit element having at least one bond site and a passivation layer. The bond site is accessible through an aperture in the passivation layer. At least two ball bumps are disposed at the bond site. A first ball bump is bonded to the bond site, and each additional ball bump is bonded on a previously bonded ball bump so that the height of the ball bumps is greater than the thickness of the passivation layer above the bond site. A ball bond is bonded to an uppermost ball bump and has a wire formed integrally therewith.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventor: Patrick Carberry
  • Publication number: 20050146413
    Abstract: Electrical devices having tunable electrical characteristics are provided, such as variable resistors, capacitors and inductors. The tunable electrical characteristics are achieved by placing an appropriate material between substrate layers and by controllably applying a pressure to the material to compress the material or alter the shape of a well in which the material is contained, and thereby alter the electrical characteristics of the electrical device. The composition, shape and dimension of the embedded materials determine how the electrical characteristics of the electrical device are altered upon compression of the embedded material in response to an applied control signal. Generally, as the embedded material is compressed, the material will become more dense and the electrical characteristics of the integrated electrical device is altered.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 7, 2005
    Inventors: Patrick Carberry, Jeffrey Gilbert