Patents by Inventor Patrick Connor

Patrick Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220279057
    Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device is to receive a request to transmit data, based on a first reliable transport protocol, and cause the data to be transmitted in at least one packet, based on a second reliable transport protocol, to a destination device and receive at least one packet, from a sender device, based on the second reliable transport protocol and indicate receipt of the at least one packet, based on the first reliable transport protocol, wherein the first reliable transport protocol is different than the second reliable transport protocol.
    Type: Application
    Filed: May 17, 2022
    Publication date: September 1, 2022
    Inventors: Patrick CONNOR, Scott P. DUBAL, James R. HEARN, Andrew J. HERDRICH, Kapil SOOD
  • Publication number: 20220149625
    Abstract: Examples described herein relate to controlling power available to processes and hardware devices to control a monetary cost of utilized electricity and/or amount of energy utilized from non-renewable energy sources. The system can modify operating configurations of processes and/or hardware based on the available power. The system can control total power drawn to control a monetary cost of power and/or avoid drawing power from non-renewable sources (e.g., fossil fuel sources or grid including gas or coal-based energy sources).
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Inventors: Akhilesh S. THYAGATURU, Saidulu ALDAS, Vinodh GOPAL, Mohit Kumar GARG, Patrick CONNOR
  • Publication number: 20220114011
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate network interface device based edge computing. A disclosed example includes threshold analyzer circuitry to identify a resource inactivity threshold for first a resource associated with the network interface device, the resource inactivity threshold indicative of a duration of time that the first resource is not utilized; resource allocator circuitry to determine that the resource meets the resource inactivity threshold; and virtual platform manager circuitry to generate a virtual platform associated with the network interface device based on the determination, the generated virtual platform to reduce latency in execution of a function.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Patrick Connor, Kevin Liedtke, Francesc Guim Bernat, James Hearn
  • Publication number: 20220103185
    Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 31, 2022
    Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
  • Patent number: 11282035
    Abstract: Systems and methods for orchestrating a process are disclosed. In an implementation, a system is configured to extract process information associated with the process. Based on the process information, the system is configured to determine a current model of performing the process based on the process information. The system is further configured to retrieve regulatory information associated with the process, wherein the regulatory information is indicative of at least one of a predefined policy, a predefined rule, and a predefined regulation associated with the process. Further, the system is configured to update the current model based on at least one of the process information and the regulatory information for obtaining a predefined outcome of the process.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: March 22, 2022
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Chung-Sheng Li, Suraj Govind Jadhav, Saurabh Mahadik, Prakash Ghatage, Guanglei Xiong, Emmanuel Munguia Tapia, Mohammad Jawad Ghorbani, Kyle Johnson, Colin Patrick Connors, Benjamin Nathan Grosof
  • Publication number: 20210405730
    Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 30, 2021
    Inventors: Brian J. Skerry, Ira Weiny, Patrick Connor, Tsung-Yuan C. Tai, Alexander W. Min
  • Publication number: 20210320870
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
  • Patent number: 11146288
    Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
  • Patent number: 11102117
    Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Iosif Gasparakis, Peter P. Waskiewicz, Jr., Patrick Connor
  • Patent number: 11070476
    Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Andrey Chilikin, Brendan Ryan, Chris MacNamara, John J. Browne, Krishnamurthy Jambur Sathyanarayana, Stephen Doyle, Tomasz Kantecki, Anthony Kelly, Ciara Loftus, Fiona Trahe
  • Publication number: 20210209035
    Abstract: Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub.
    Type: Application
    Filed: March 25, 2021
    Publication date: July 8, 2021
    Inventors: Duane E. GALBI, Matthew J. ADILETTA, Hugh WILKINSON, Patrick CONNOR
  • Patent number: 11054884
    Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Brian J. Skerry, Ira Weiny, Patrick Connor, Tsung-Yuan C. Tai, Alexander W. Min
  • Patent number: 11036531
    Abstract: Examples may include techniques to live migrate a virtual machine (VM) using disaggregated computing resources including compute and memory resources. Examples include copying data between allocated memory resources that serve as near or far memory for compute resources supporting the VM at a source or destination server in order to initiate and complete the live migration of the VM.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Connor, James R. Hearn, Scott P. Dubal, Andrew J. Herdrich, Kapil Sood
  • Publication number: 20210157935
    Abstract: A network interface controller (NIC) to interact with virtual environments (e.g., virtual machines, containers) when they are within a trusted environment protected by a cryptography scheme.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Inventors: Kapil SOOD, Patrick CONNOR
  • Patent number: 10860374
    Abstract: In one embodiment, a system comprises platform logic comprising a plurality of processor cores and resource allocation logic. The resource allocation logic may receive a processing request and direct the processing request to a processor core of the plurality of processor cores, wherein the processor core is selected based at least in part on telemetry data associated with the platform logic, the telemetry data indicating a topology of at least a portion of the platform logic.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: James Robert Hearn, Patrick Connor, Kapil Sood, Scott P. Dubai, Andrew J. Herdrich
  • Publication number: 20200322287
    Abstract: Examples described herein relate to a switch device for a rack of two or more physical servers, wherein the switch device is coupled to the two or more physical servers and the switch device performs packet protocol processing termination for received packets and provides payload data from the received packets without a received packet header to a destination buffer of a destination physical server in the rack. In some examples, the switch device comprises at least one central processing unit, the at least one central processing unit is to execute packet processing operations on the received packets. In some examples, a physical server executes at least one virtualized execution environments (VEE) and the at least one central processing unit executes a VEE for packet processing of packets with data to be accessed by the physical server that executes the VEE.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Patrick CONNOR, James R. HEARN, Kevin LIEDTKE, Scott P. DUBAL
  • Publication number: 20200301864
    Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: INTEL CORPORATION
    Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
  • Publication number: 20200280324
    Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 3, 2020
    Inventors: Patrick Connor, Kapil Sood, Scott Dubal, Andrew Herdrich, James Hearn
  • Publication number: 20200259763
    Abstract: Examples described herein relate to a device configured to allocate memory resources for packets received by the network interface based on received configuration settings. In some examples, the device is a network interface. Received configuration settings can include one or more of: latency, memory bandwidth, timing of when the content is expected to be accessed, or encryption parameters. In some examples, memory resources include one or more of: a cache, a volatile memory device, a storage device, or persistent memory. In some examples, based on a configuration settings not being available, the network interface is to perform one or more of: dropping a received packet, store the received packet in a buffer that does not meet the configuration settings, or indicate an error. In some examples, configuration settings are conditional where the settings are applied if one or more conditions is met.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Francesc GUIM BERNAT, Patrick CONNOR, Patrick G. KUTCH, John J. BROWNE, Alexander BACHMUTSKY
  • Patent number: 10739850
    Abstract: Systems and methods for tracking gaze information of a user includes detecting, by a sensor of a head mounted display, that a user is wearing the HMD. An encoded signal indicative of glasses being worn with the HMD, by the user, is detected by the sensor of the HMD. In response to processing the encoded signal, a gaze detection function of the HMD is disabled by the HMD. Encoded gaze data transmitted by the glasses is received by the HMD. The encoded gaze data is processed by an image frame processor and used to adjust image frames produced for rendering on a display screen of the HMD.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 11, 2020
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Jeffrey Roger Stafford, Christopher Norden, Patrick Connor