Patents by Inventor Patrick Connor

Patrick Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190044812
    Abstract: Technologies for dynamically selecting resources for virtual switching include a network appliance configured to identify a present demand on processing resources of the network appliance that are configured to process data associated with network packets received by the network appliance. Additionally, the network appliance is configured to determine a present capacity of one or more acceleration resources of the network appliance and determine a virtual switch operation mode based on the present demand and the present capacity of the acceleration resources, wherein the virtual switch operation mode indicates which of the acceleration resources are to be enabled. The network appliance is additionally configured to configure a virtual switch of the network appliance to operate as a function of the determined virtual switch operation mode and assign acceleration resources of the network appliance as a function of the determined virtual switch operation mode. Other embodiments are described herein.
    Type: Application
    Filed: September 13, 2018
    Publication date: February 7, 2019
    Inventors: Ciara Loftus, Chris MacNamara, John J. Browne, Patrick Fleming, Tomasz Kantecki, John Barry, Patrick Connor
  • Publication number: 20190044893
    Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.
    Type: Application
    Filed: June 30, 2018
    Publication date: February 7, 2019
    Inventors: Bruce Richardson, Chris MacNamara, Patrick Fleming, Tomasz Kantecki, Ciara Loftus, John J. Browne, Patrick Connor
  • Publication number: 20190044879
    Abstract: Technologies for reordering network packets on egress include a network interface controller (NIC) configured to associate a received network packet with a descriptor, generate a sequence identifier for the received network packet, and insert the generated sequence identifier into the associated descriptor. The NIC is further configured to determine whether the received network packet is to be transmitted from a compute device associated with the NIC to another compute device and insert, in response to a determination that the received network packet is to be transmitted to the another compute device, the descriptor into a transmission queue of descriptors. Additionally, the NIC is configured to transmit the network packet based on position of the descriptor in the transmission queue of descriptors based on the generated sequence identifier. Other embodiments are described herein.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Inventors: Bruce Richardson, Andrew Cunningham, Alexander J. Leckey, Brendan Ryan, Patrick Fleming, Patrick Connor, David Hunt, Andrey Chilikin, Chris MacNamara
  • Publication number: 20190044860
    Abstract: Technologies for providing adaptive polling of packet queues include a compute device. The compute device includes a network interface controller and a compute engine that includes a set of cores and a memory that includes a queue to store packets received by the network interface controller. The compute engine is configured to determine a predicted time period for the queue to receive packets without overflowing, execute, during the time period and with a core that is assigned to periodically poll the queue for packets, a workload, and poll, with the assigned core, the queue to remove the packets from the queue. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 18, 2018
    Publication date: February 7, 2019
    Inventors: Chris MacNamara, John Browne, Tomasz Kantecki, Ciara Loftus, John Barry, Patrick Connor, Patrick Fleming
  • Patent number: 10174407
    Abstract: A titanium alloy comprising an elevated level of oxygen is disclosed. The alloy may have 5.5 to 6.75 weight percent of aluminum, 3.5 to 4.5 weight percent of vanadium, 0.21 to 0.30 weight percent of oxygen, and up to 0.40% of weight percent of iron. The alloy may also have a minimum ultimate tensile strength of 130,000 psi, a minimum tensile yield strength of 120,000 psi, and a minimum ductility of 10% elongation. Also disclosed is a method for manufacturing components having the aforementioned alloy.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 8, 2019
    Assignee: Arconic Inc.
    Inventors: Stanley Abkowitz, Susan M. Abkowitz, Patrick Connors, David Main, Harvey Fisher
  • Publication number: 20190005590
    Abstract: A system for orchestrating an operation is disclosed. The system includes an case orchestration engine to identify a discrepancy in the operation, and to generate a plurality of hypotheses for resolving the discrepancy. The case orchestration engine further collects evidence pertaining to the discrepancy in the operation, evaluates each of the plurality of hypotheses based on a dialogue-driven feedback received from a user, and selects one of the plurality of hypotheses for resolving the discrepancy based on the evidence and an expected outcome of the operation. The case orchestration engine provides reasons for the discrepancy along with remedial measures for resolving the discrepancy based on the selected hypothesis, and then generates a plan for performing the operation to achieve the expected outcome based on the remedial measures.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Chung-Sheng LI, Suraj Govind JADHAV, Saurabh MAHADIK, Prakash GHATAGE, Guanglei XIONG, Emmanuel MUNGUIA TAPIA, Mohammad Jawad GHORBANI, Kyle JOHNSON, Colin Patrick CONNORS, Benjamin Nathan GROSOF
  • Publication number: 20180374051
    Abstract: Systems and methods for orchestrating a process are disclosed. In an implementation, a system is configured to extract process information associated with the process. Based on the process information, the system is configured to determine a current model of performing the process based on the process information. The system is further configured to retrieve regulatory information associated with the process, wherein the regulatory information is indicative of at least one of a predefined policy, a predefined rule, and a predefined regulation associated with the process. Further, the system is configured to update the current model based on at least one of the process information and the regulatory information for obtaining a predefined outcome of the process.
    Type: Application
    Filed: June 21, 2017
    Publication date: December 27, 2018
    Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Chung-Sheng LI, Suraj Govind JADHAV, Saurabh MAHADIK, Prakash GHATAGE, Guanglei XIONG, Emmanuel Munguia TAPIA, Mohammad Jawad GHORBANI, Kyle JOHNSON, Colin Patrick CONNORS, Benjamin Nathan GROSOF
  • Publication number: 20180373553
    Abstract: Examples may include techniques to live migrate a virtual machine (VM) using disaggregated computing resources including compute and memory resources. Examples include copying data between allocated memory resources that serve as near or far memory for compute resources supporting the VM at a source or destination server in order to initiate and complete the live migration of the VM.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Inventors: Patrick CONNOR, James R. Hearn, Scott P. DUBAL, Andrew J. HERDRICH, Kapil SOOD
  • Patent number: 10091063
    Abstract: Technologies to monitor and manage platform, device, processor and power characteristics throughout a system utilizing a remote entity such as controller node. By remotely monitoring and managing system operation and performance over time, future system performance requirements may be anticipated, allowing system parameters to be adjusted proactively in a more coordinated way. The controller node may monitor, control and predict traffic flows in the system and provide performance modification instructions to any of the computer nodes and a network switch to better optimize performance. The target systems collaborate with the controller node by respectively monitoring internal resources, such as resource availability and performance requirements to provide necessary resources for optimizing operating parameters of the system.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: October 2, 2018
    Assignee: INTEL CORPORATION
    Inventors: Alexander W. Min, Ira Weiny, Patrick Connor, Jr-Shian Tsai, Tsung-Yuan C. Tai, Brian J. Skerry, Jr., Iosif Gasparakis, Steven R. Carbonari, Daniel J. Dahle, Thomas M. Slaight, Nrupal R. Jani
  • Patent number: 10063446
    Abstract: Methods and apparatus for collection of Netflow data and export offload using network silicon. In accordance with aspects of the embodiments, the Netflow export and collection functions are offloaded to the network silicon in the chipset, System on a Chip (SoC), backplane switch, disaggregated switch, virtual switch (vSwitch) accelerator, and Network Interface Card/Controller (NIC) level. For apparatus implementing virtualized environments, one or both of the collection and export functions are implemented at the Physical Function (PF) and/or Virtual Function (VF) layers of the apparatus.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Scott P. Dubal, James R. Hearn, Patrick Connor
  • Publication number: 20180181421
    Abstract: An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Inventors: Patrick Connor, Scott P. Dubal, James R. Hearn, Iosif Gasparakis, Chris Pavlas, Eliezer Tamir
  • Publication number: 20180173580
    Abstract: Methods and apparatus to recover a processor state during a system failure or security event are disclosed. An example apparatus to recover data includes a processor including a local memory and a system monitor in communication with the processor. The system monitor is to copy processor backup data to a non-volatile memory in response to a processor backup event. The processor backup data includes contents of the local memory.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Inventors: Chris Pavlas, James R. Hearn, Scott P. Dubal, Patrick Connor
  • Publication number: 20180164868
    Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Applicant: Intel Corporation
    Inventors: Brian J. Skerry, Ira Weiny, Patrick Connor, Tsung-Yuan C. Tai, Alexander W. Min
  • Publication number: 20180150654
    Abstract: Examples include techniques for a field programmable gate array (FPGA) to perform one or more functions for an application specific integrated circuit (ASIC). Example techniques include communication between the ASIC and the FPGA via a sideband communication link to enable the ASIC to indicate to the FPGA a need for the FPGA to perform a function to fulfill a request received by the ASIC.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Applicant: Intel Corporation
    Inventors: Patrick Connor, Scott P. Dubal, Sridhar Samudrala, Praveen Mala, Sibai Li
  • Patent number: 9985886
    Abstract: Technologies for pacing transmission of network packets by a computing device to a remote computing device include performing a segmentation offload operation to segment a payload of a network packet into a plurality of network packet segments in response to a determination that a size of the payload is greater than a maximum allowable payload size. The computing device additionally determines a packet pacing interval and transmits the plurality of network packet segments to the remote computing device at a transmission rate based on the packet pacing interval.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Jesse C. Brandeburg, Scott P. Dubal, Patrick Connor, David E. Cohen
  • Patent number: 9846576
    Abstract: Technologies for reprogramming/updating non-volatile memory (NVM) for a peripheral, such as a network interface controller (NIC). Communications are provided in the NIC for communicating data to and from a network from a computer node, along with a controller operatively coupled to the communications for controlling the communication of data. A NIC access redirection agent module is configured to accesses a NVM firmware image from the network via the communications to reprogram and/or update the NIC, wherein the accessed NVM firmware image is utilized by the computer node NIC for operation. A network node may include a firmware manager for selecting one of a plurality of NVM firmware images and provide access to the selected NVM firmware image for the computer node to update computer node firmware for the computing device over the computer network.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Scott P. Dubal, Patrick Connor
  • Patent number: 9826656
    Abstract: The present disclosure describes embodiments of apparatuses and methods related to a moveable server rack in a data center. The server rack may include a chassis with a plurality of servers and a receptacle to couple with a mobile robot. The mobile robot may move the server rack from a first location to a second location in a data center. The server rack may include indices of alignment to provide an indication of docking alignment of the server rack to at least the second docking location, a power connector system to connect a main power source to the plurality of servers at the second location, and an input/output connector to connect a data center network to the plurality of servers at the second location. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Patrick Connor, Scott P. Dubal, James R. Hearn
  • Patent number: 9769050
    Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Patrick Connor, Dinesh Kumar, Alexander W. Min, Ravishankar Iyer, Daniel J. Dahle, Kapil Sood, Jeffrey B. Shaw
  • Patent number: 9712337
    Abstract: Methods and apparatus for implementing Power over Ethernet (PoE) for auxiliary power in computer systems. Under aspects of the methods, one or more voltage inputs comprising standard power input is employed by a power control component in a network interface in an apparatus such as a network adaptor board, a System on a Chip (SoC), computer server or server blade to supply power to a network controller on the apparatus when the apparatus is operating at a normal power state. To enable the apparatus to maintain network communication when operating at a reduced power state, a PoE power input derived from at least one PoE signal received at at least one Ethernet jack of the apparatus is employed to provide power to the network controller absent use or availability of the standard power input. Accordingly, the PoE power input facilitates an auxiliary power function that may be used alone or in combination with existing (as applicable) auxiliary power input when apparatus are operated in reduced power states.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Paul Greenwalt, Patrick Connor, Scott P. Dubal, Chris Pavlas
  • Publication number: 20170155717
    Abstract: Embodiments of the disclosure are directed to controlling an endpoint device running an endpoint device using a central control server. The central controller server is configured to communicate with the endpoint device across a communications interface compliant with a remote direct access (RDMA) compliant protocol. The central control server includes an RDMA network interface controller and a control process. The control process can execute an endpoint device algorithm to identify read and write commands to be sent across the RDMA protocol-compliant interface to the endpoint device. The RDMA network interface controller can convert messages into RDMA compliant messages that include direct read or write commands and memory location information. The endpoint device can also include a network interface controller that can understand the RDMA message, identify the memory location from the message, and execute the direct read or write access command.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Applicant: Intel Corporation
    Inventors: Eliezer Tamir, Patrick Connor