Patents by Inventor Patrick Conway

Patrick Conway has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180342050
    Abstract: There is presented a system and method for detecting mobile device fault conditions, including detecting fault conditions by software operating on the mobile device. In one embodiment, the present invention provides for systems and methods for using a neural network to detect, from an image of the device, that the mobile device has a defect, for instance a cracked or scratched screen. Systems and methods also provide for, reporting the defect status of the device, working or not, so that appropriate action may be taken by a third party.
    Type: Application
    Filed: February 19, 2018
    Publication date: November 29, 2018
    Applicant: YOUGETITBACK Limited
    Inventors: William Fitzgerald, Donal O'Shaughnessy, Donie Kelly, Paul O'Sullivan, Liam O'Callaghan, James Donavan, Shane Hallinan, Charlie McGrory, Wayne Morgan, Uday Chitturi, Patrick Conway, John Mollaghan, Kevin Sutton
  • Patent number: 9933523
    Abstract: There is disclosed systems and methods to enhance reliability of measured position data. Measuring devices, such mobile phones equipped with location measurement elements (such as GPS, LBS, network location reporting, or tower location triangulation reporting) may collect various samples of positions where the device is believed to be located at particular moments in time; however such measurements often vary even if the device is not moving because of device inaccuracy, atmospheric conditions, obstructing buildings, and the like, making it difficult to determine whether such devices are actually stationary or are in motion over predetermined time periods. Systems and methods of the present invention provide for enhanced accuracy of position data by selectively merging varying location positions that are attributable to noise or accuracy deviations, and providing an enhanced assessment of actual device position.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: April 3, 2018
    Assignee: YOUGETITBACK LIMITED
    Inventors: William Fitzgerald, Patrick Conway, Peter Bermingham
  • Publication number: 20170349975
    Abstract: The present invention relates to metal alloys including copper.
    Type: Application
    Filed: October 27, 2015
    Publication date: December 7, 2017
    Inventors: Kevin Laws, Michael Ferry, Patrick Conway, Warren McKenzie, Lori Bassman, Cody Crosby, Aarthi Sridhar
  • Patent number: 9507715
    Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: November 29, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric Morton, Patrick Conway, Elizabeth Morrow Cooper, Vydhyanathan Kalyanasundharam
  • Publication number: 20160117179
    Abstract: A command replacement module at a coherency manager of a processor receives commands to be communicated over the communication fabric. For each received command of a specified type, the command replacement module compares a data payload of the command to a stored set of data patterns and, in response to a match, replaces the command with a replacement command, wherein the replacement command implies the contents of the data payload. The replacement command is communicated to the original commands destination via the communication fabric. In response to receiving the replacement command, the destination reconstructs the original command, deriving the data payload from the replacement command.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Inventors: Eric Morton, Patrick Conway, Greggory Douglas Donley, Vydhyanathan Kalyanasundharam
  • Publication number: 20160117247
    Abstract: A processor accumulating coherency probe responses, thereby reducing the impact of coherency messages on the bandwidth of the processor's communication fabric. A probe response accumulator is connected to a processing module of the processor, the processing module having multiple processor cores and associated caches. In response to a coherency probe, the processing module generates a different coherency probe response for each of the caches. The probe response accumulator combines the different coherency probe responses into a single coherency probe response and communicates the single coherency response over the communication fabric.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Inventors: Eric Morton, Patrick Conway, Alan Dodson Smith, Greggory Douglas Donley, Vydhyanathan Kalyanasundharam
  • Publication number: 20160117248
    Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 28, 2016
    Inventors: Eric Morton, Patrick Conway, Elizabeth Morrow Cooper, Vydhyanathan Kalyanasundharam
  • Publication number: 20140159952
    Abstract: There is disclosed systems and methods to enhance reliability of measured position data. Measuring devices, such mobile phones equipped with location measurement elements (such as GPS, LBS, network location reporting, or tower location triangulation reporting) may collect various samples of positions where the device is believed to be located at particular moments in time; however such measurements often vary even if the device is not moving because of device inaccuracy, atmospheric conditions, obstructing buildings, and the like, making it difficult to determine whether such devices are actually stationary or are in motion over predetermined time periods. Systems and methods of the present invention provide for enhanced accuracy of position data by selectively merging varying location positions that are attributable to noise or accuracy deviations, and providing an enhanced assessment of actual device position.
    Type: Application
    Filed: August 16, 2013
    Publication date: June 12, 2014
    Inventors: William Fitzgerald, Patrick Conway, Peter Bermingham
  • Patent number: 8478942
    Abstract: A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 2, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick Conway
  • Patent number: 8360675
    Abstract: Embodiments described herein relate to dividers and folders with tabs adjustable along at least two edges thereof. One embodiment is directed to a folder comprising a first panel, a second panel coupled to the first panel, at least one tab mating feature associated with the second panel, and a tab configured to mate with the at least one tab mating feature. The at least one tab mating feature is configured such that the tab is positionable in at least two positions along a first axis adjacent a first edge of the second panel and in at least two positions along a second axis adjacent a second edge of the second panel, wherein the first axis is transverse to the second axis.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: January 29, 2013
    Assignee: Staples The Office Superstore, LLC
    Inventors: Michael Kent, Chad Kendall, Kara Brunetta, Patrick Conway, Irene Wong
  • Patent number: 8185695
    Abstract: A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of a shared cache memory subsystem, such as an L3 cache. Directory entries are stored within the shared cache memory subsystem to provide indications of lines (or blocks) that may be cached in exclusive-modified, owned, shared, shared-one, or invalid coherency states. The absence of a directory entry for a particular line may imply that the line is not cached anywhere in a computing system.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Patrick Conway, Kevin Michael Lepak
  • Publication number: 20120079205
    Abstract: A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 29, 2012
    Inventor: Patrick Conway
  • Patent number: 7930485
    Abstract: A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: April 19, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Michael K Fertig, Patrick Conway, Kevin Michael Lepak, Cissy Xumin Yuan
  • Patent number: 7882327
    Abstract: In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, William A. Hughes, Patrick Conway, Jeffrey Dwork
  • Publication number: 20100123013
    Abstract: A thermostatic mixing valve having a hot water inlet for connection to a supply of hot water, a cold water inlet for connection to a supply of cold water, an outlet for temperature controlled water and a valve device for controlling the relative proportions of hot and cold water admitted to a mixing chamber. The outlet communicates with the mixing chamber to receive temperature controlled water having a desired temperature. A temperature control adjusts the valve device in accordance with the desired temperature of the temperature controlled water where the valve device and the mixing chamber form flow passages for the incoming streams of hot and cold water and are configured such that the velocity of the incoming water streams is maintained and the incoming water streams are turned to flow in the same direction so that flow of one stream can entrain and assist flow of the other stream.
    Type: Application
    Filed: January 14, 2010
    Publication date: May 20, 2010
    Applicant: Kohler Mira Limited
    Inventors: Nicholas John Beck, Sean Patrick Conway, Bruce Lewin John Hayward, Kevin Taylor Peel
  • Publication number: 20100116872
    Abstract: Embodiments described herein relate to dividers and folders with tabs adjustable along at least two edges thereof. One embodiment is directed to a folder comprising a first panel, a second panel coupled to the first panel, at least one tab mating feature associated with the second panel, and a tab configured to mate with the at least one tab mating feature. The at least one tab mating feature is configured such that the tab is positionable in at least two positions along a first axis adjacent a first edge of the second panel and in at least two positions along a second axis adjacent a second edge of the second panel, wherein the first axis is transverse to the second axis.
    Type: Application
    Filed: September 21, 2009
    Publication date: May 13, 2010
    Applicant: Staples The Office Superstore, LLC
    Inventors: Michael Kent, Chad Kendall, Kara Brunetta, Patrick Conway, Irene Wong
  • Patent number: 7669776
    Abstract: A thermostatic mixing valve for hot and cold water has two-stage inlet chambers for the hot and cold water flows respectively. The inlet chambers distribute the flows uniformly with respect to porting for admitting the flows to the mixing chamber to reduce asymmetric flow patterns and promote thorough mixing of the flows within the mixing chamber.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: March 2, 2010
    Assignee: Kohler Mira Limited
    Inventors: Nicholas John Beck, Sean Patrick Conway, Bruce Lewin John Hayward, Kevin Taylor Peel
  • Publication number: 20090327616
    Abstract: A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of a shared cache memory subsystem, such as an L3 cache. Directory entries are stored within the shared cache memory subsystem to provide indications of lines (or blocks) that may be cached in exclusive-modified, owned, shared, shared-one, or invalid coherency states. The absence of a directory entry for a particular line may imply that the line is not cached anywhere in a computing system.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Patrick Conway, Kevin Michael Lepak
  • Publication number: 20090037688
    Abstract: In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: Vydhyanathan Kalyanasundharam, William A. Hughes, Patrick Conway, Jeffrey Dwork
  • Publication number: 20090024835
    Abstract: A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Inventors: Michael K. Fertig, Patrick Conway, Kevin Michael Lepak, Cissy Xumin Yuan