Abstract: A data processing system (100, 600) has a memory hierarchy including a cache (124, 624) and a lower-level memory system (170, 650). A data element having a special write with inject attribute is received from a data producer (160, 640), such as an Ethernet controller. The data element is forwarded to the cache (124, 624) without accessing the lower-level memory system (170, 650). Subsequently at least one cache line containing the data element is updated in the cache (124, 624).

Abstract: A data processor (120) recognizes a special data processing operation in which data will be stored in a cache (124) for one use only. The data processor (120) allocates a memory location to at least one cache line of the cache (124). A data producer such as a data communication driver program running on a central processing unit (122) then writes a data element to the allocated memory location. A data consumer (160) reads the data element by sending a READ ONCE request to a host bridge (130). The host bridge (130) provides the READ ONCE request to a memory controller (126), which reads the data from the cache (124) and de-allocates the at least one cache line without performing a writeback from the cache to a main memory (170). In one form the memory controller (126) de-allocates the at least one cache line by issuing a probe marking the next state of the associated cache line as invalid.

Abstract: A thermostatic mixing valve for hot and cold water has two-stage inlet chambers for the hot and cold water flows respectively. The inlet chambers distribute the flows uniformly with respect to porting for admitting the flows to the mixing chamber to reduce asymmetric flow patterns and promote thorough mixing of the flows within the mixing chamber.

Abstract: A water supply installation for ablutionary appliances has a mixer valve for mixing and blending hot and cold water in accordance with user selection of water temperature and a damping chamber downstream of the mixer valve for reducing transient temperature overshoots when the selected water temperature is changed.

Abstract: In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i.e., it does not rely on immediately preceding write to determine where the data packet should be sent. Using “address aliasing”, CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.