Abstract: Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which solve the above problems using a global shared region of memory that combines memory segments from multiple CXL devices. Each memory segment is a same size and naturally aligned in its own physical address space. The global shared region is contiguous and naturally aligned in the virtual address space. By organizing this global shared region in this manner, a series of three tables may be used to quickly translate a virtual address in the global shared region to a physical address. This prevents TLB thrashing and improves performance of the computing system.

Abstract: A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.

Abstract: Devices and techniques for triggering early termination of cooperating processes in a processor are described herein. A system includes multiple memory-compute nodes, wherein a memory-compute node comprises: event manager circuitry configured to establish a broadcast channel to receive event messages; and thread manager circuitry configured to organize a plurality of threads to perform portions of a cooperative task, wherein the plurality of threads each monitor the broadcast channel to receive event messages on the broadcast channel, and wherein upon achieving a threshold operation, the thread manager circuitry is to use the event manager circuitry to broadcast, on the broadcast channel, an event message indicating that the cooperative task is complete, causing other threads, in response to receiving the event message, to terminate execution of their respective portions of the cooperative task.

Abstract: A memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. The memory controller can include interface management circuitry coupled to a cache and a memory device. The memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. The memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. The memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.

Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums that provide a memory allocation mechanism that evenly spreads the allocations for an application over all the MCs on the system, thus minimizing congestion and resulting in optimal application performance.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

Abstract: There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

Abstract: Devices and techniques for triggering early termination of cooperating processes in a processor are described herein. A system includes multiple memory-compute nodes, wherein a memory-compute node comprises: event manager circuitry configured to establish a broadcast channel to receive event messages; and thread manager circuitry configured to organize a plurality of threads to perform portions of a cooperative task, wherein the plurality of threads each monitor the broadcast channel to receive event messages on the broadcast channel, and wherein upon achieving a threshold operation, the thread manager circuitry is to use the event manager circuitry to broadcast, on the broadcast channel, an event message indicating that the cooperative task is complete, causing other threads, in response to receiving the event message, to terminate execution of their respective portions of the cooperative task.

Abstract: Devices and techniques for neural network transpose layer removal are described herein. A neural network model that includes matrices of synaptic weights arranged in several layers is obtained. The neural network model is inspected to determine whether a transposition of a matrix to a fully connected layer exists. If there is a matrix transposition, then a modified neural network model is created by changing values of the fully connected layer to correspond to values in the matrix prior to the transposition and eliminating the transposition. The modified neural network model can then be provided to computer hardware to perform inference operations.

Abstract: Devices and techniques for providing receipts for event messages in a processor are described herein. A system includes multiple memory-compute nodes coupled to one another over a scale fabric; a set of registers; and an event manager hardware circuitry to: receive an event message corresponding to an event, and the event associated with an event mode; track a counter value representing a number of received event messages related to the event, the counter value stored in the set of registers; compare the number of received event messages to a trigger value; and in response to the number of received event messages equaling the trigger value: use an atomic operation to reset the counter value in the set of registers while maintaining the event mode; and alert a thread of the event.

Abstract: Devices and techniques for CHAINED RESOURCE LOCKING are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread’s identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.

Abstract: A hybrid threading processor (HTP) supports thread creation by executing an instruction that indicates an amount of storage space to reserve for return values. Before a thread is created, the indicated amount of space is reserved. The newly created child thread sends a return packet back to the parent thread when the child thread completes. The thread writes its return information into the reserved space and waits for the parent thread to execute a thread join instruction. The thread join instruction takes the returned information from the reserved space and transfers it to the parent thread's register state. The reserved space is released once the child thread is joined. Using a configurable amount of space for each child thread may allow for more child threads to be executed simultaneously.

Abstract: Devices and techniques for triggering early termination of cooperating processes in a processor are described herein. A system includes multiple memory-compute nodes, wherein a memory-compute node comprises: event manager circuitry configured to establish a broadcast channel to receive event messages; and thread manager circuitry configured to organize a plurality of threads to perform portions of a cooperative task, wherein the plurality of threads each monitor the broadcast channel to receive event messages on the broadcast channel, and wherein upon achieving a threshold operation, the thread manager circuitry is to use the event manager circuitry to broadcast, on the broadcast channel, an event message indicating that the cooperative task is complete, causing other threads, in response to receiving the event message, to terminate execution of their respective portions of the cooperative task.

Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums that provide a memory allocation mechanism that evenly spreads the allocations for an application over all the MCs on the system, thus minimizing congestion and resulting in optimal application performance.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that use parallel hardware execution with software co-simulation to enable more advanced debugging operations on data flow architectures. Upon a halt to execution of a program thread, a state of the tiles that are executing the thread are saved and offloaded from the HTF to a host system. A developer may then examine this state on the host system to debug their program. Additionally, the state may be loaded into a software simulator that simulates the HTF hardware. This simulator allows for the developer to step through the code and to examine values to find bugs.

Abstract: A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.