Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which solve the above problems using a global shared region of memory that combines memory segments from multiple CXL devices. Each memory segment is a same size and naturally aligned in its own physical address space. The global shared region is contiguous and naturally aligned in the virtual address space. By organizing this global shared region in this manner, a series of three tables may be used to quickly translate a virtual address in the global shared region to a physical address. This prevents TLB thrashing and improves performance of the computing system.

Abstract: Devices and techniques for neural network transpose layer removal are described herein. A neural network model that includes matrices of synaptic weights arranged in several layers is obtained. The neural network model is inspected to determine whether a transposition of a matrix to a fully connected layer exists. If there is a matrix transposition, then a modified neural network model is created by changing values of the fully connected layer to correspond to values in the matrix prior to the transposition and eliminating the transposition. The modified neural network model can then be provided to computer hardware to perform inference operations.

Abstract: There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.

Abstract: Devices and techniques for providing receipts for event messages in a processor are described herein. A system includes multiple memory-compute nodes coupled to one another over a scale fabric; a set of registers; and an event manager hardware circuitry to: receive an event message corresponding to an event, and the event associated with an event mode; track a counter value representing a number of received event messages related to the event, the counter value stored in the set of registers; compare the number of received event messages to a trigger value; and in response to the number of received event messages equaling the trigger value: use an atomic operation to reset the counter value in the set of registers while maintaining the event mode; and alert a thread of the event.

Abstract: System and techniques for performing a reduction operation using event hardware are described herein. In an environment in which sub-processes are run on different processors, and these sub-processes inform a head process via event messaging, when a reduction operation is completed by a sub-process of the sub-processes, the partial result of the sub-process is received at event management circuitry of the processor of the head process. The event management circuitry uses the partial result to update an incremental result to the reduction operation as each sub-process result event message is received.

Abstract: Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.

Abstract: In some implementations, an emulation system may store a set of data to a first memory copy location of an emulated environment that is associated with a first virtual host system. The emulation system may copy the set of data from the first memory copy location to a shared memory location of the emulated environment. The emulation system may copy the set of data from the shared memory location to a second memory copy location of the emulated environment that is associated with a second virtual host system. The emulation system may load the set of data from the second memory copy location.

Abstract: Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.

Abstract: Apparatus and methods are disclosed, including sending, by an application executing on a processor of a computing system to a dynamic random access memory (DRAM), a memory operation indicating a DRAM cache line stored in the DRAM; receiving, by the processor, DRAM metadata stored in the DRAM for the DRAM cache line; identifying, by the processor, a tiered memory region of multiple tiered memory regions storing a tiered memory cache line containing target data of the memory operation when the DRAM metadata indicates that the target data is not stored in the DRAM cache line; and loading the tiered memory cache line containing the target data into the DRAM, loading the DRAM cache line into the identified tiered memory region, and updating the DRAM metadata.

Abstract: A processing device in a system receives a first request for a first set of memory addresses. The processing device determines, based on the first request, whether to assign a first set of physical addresses of a portion of physical addresses of a memory device as the first set of memory addresses. Responsive to determining not to assign the first set of physical addresses, the processing device requests a first set of virtual addresses of a plurality of contiguous virtual addresses. A first portion of virtual addresses of the plurality of contiguous virtual addresses contiguously maps to a second portion of physical addresses of the memory device. The processing device stores data to a second set of physical addresses contiguously mapped to the first set of virtual addresses.

Abstract: A processing device in a memory sub-system receives a first set of requests to access first data stored at a first set of physical addresses. The processing device identifies, using a physical address table comprising information about (i) a host and (ii) an application assigned to respective sets of physical addresses, a first host identity and a first application identity corresponding to the first set of physical addresses. The processing device further provides the first set of requests, the first host identity and the first application identity to a prefetch prediction engine. The processing device receives an output of the prefetch prediction engine, the output comprising a first memory address for prefetching second data from the first set of physical addresses to fulfill a second set of requests.

Abstract: Systems, apparatuses, and methods related to data reconstruction based on queue depth comparison are described. To avoid accessing the “congested” channel, a read command to access the “congested” channel can be executed by accessing the other relatively “idle” channels and utilize data read from the “idle” channels to reconstruct data corresponding to the read command.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

Abstract: Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.

Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Abstract: Systems, apparatuses, and methods related to data reconstruction based on queue depth comparison are described. To avoid accessing the “congested” channel, a read command to access the “congested” channel can be executed by accessing the other relatively “idle” channels and utilize data read from the “idle” channels to reconstruct data corresponding to the read command.

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request/response buffer sets, and each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups.

Abstract: Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.

Abstract: Devices and techniques for chained resource locking are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread's identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.

Abstract: Linear interpolation is performed within a memory system. The memory system receives a floating-point point index into an integer-indexed memory array. The memory system accesses the two values of the two adjacent integer indices, performs the linear interpolation, and provides the resulting interpolated value. In many system architectures, the critical limitation on system performance is the data transfer rate between memory and processing elements. Accordingly, reducing the amount of data transferred improves overall system performance and reduces power consumption.