Patents by Inventor Patrick Estep

Patrick Estep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220317972
    Abstract: Devices and techniques for hardware for concurrent SINE and cosine determination are described herein. A first sequence of bits representing an angle of a line from an origin to a unit circle can be obtained. A quadrant of the unit circle for the line is determined and the two least significant bits of the first sequence of bits is replaced with an encoding for the quadrant, the angle is translated to a base quadrant angle and sin and cosine operations are performed on a portion of a second sequence of bits (derived from the first sequence of bits) to create intermediate sin and cosine solutions in the base quadrant. The quadrant encoding in the first sequence of bits is then used to create a final sin and cosine solutions in the quadrant from the intermediate solutions.
    Type: Application
    Filed: August 18, 2021
    Publication date: October 6, 2022
    Inventors: Douglas Vanesko, Tony M. Brewer, Bryan Hornung, Patrick Estep
  • Publication number: 20220318162
    Abstract: Linear interpolation is performed within a memory system. The memory system receives a floating-point point index into an integer-indexed memory array. The memory system accesses the two values of the two adjacent integer indices, performs the linear interpolation, and provides the resulting interpolated value. In many system architectures, the critical limitation on system performance is the data transfer rate between memory and processing elements. Accordingly, reducing the amount of data transferred improves overall system performance and reduces power consumption.
    Type: Application
    Filed: April 26, 2021
    Publication date: October 6, 2022
    Inventors: Bryan Hornung, Tony M. Brewer, Douglas Vanesko, Patrick Estep
  • Publication number: 20220206846
    Abstract: Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.
    Type: Application
    Filed: September 2, 2021
    Publication date: June 30, 2022
    Inventors: Skyler Arron Windh, Tony M. Brewer, Patrick Estep
  • Publication number: 20220206804
    Abstract: Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.
    Type: Application
    Filed: August 18, 2021
    Publication date: June 30, 2022
    Inventors: Douglas Vanesko, Bryan Hornung, Patrick Estep
  • Patent number: 10042682
    Abstract: A send buffer is allocated within a kernel of an operating system (OS) of a first node. An application of the first node includes an application buffer. A message of an application buffer is copied to the send buffer. The kernel of the first node is to aggregate a plurality of the messages stored at the send buffer into a single transfer and to output the single transfer across a network to a second node.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 7, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Patrick Estep
  • Publication number: 20170004028
    Abstract: A send buffer is allocated within a kernel of an operating system (OS) of a first node. An application of the first node includes an application buffer. A message of an application buffer is copied to the send buffer. The kernel of the first node is to aggregate a plurality of the messages stored at the send buffer into a single transfer and to output the single transfer across a network to a second node.
    Type: Application
    Filed: January 30, 2014
    Publication date: January 5, 2017
    Inventor: Patrick Estep
  • Publication number: 20060059257
    Abstract: Message queue tuning is disclosed. A communication routine is provided that is able to record a log entry for a message. A log is obtained by running a software application with the communication routine. The log is evaluated to determine a desired value of a tuning knob for a message queue parameter of the communication routine, and the tuning knob is adjusted to the desired value for running the software application with the communication routine.
    Type: Application
    Filed: September 14, 2004
    Publication date: March 16, 2006
    Inventors: Jean-Francois Collard, Patrick Estep