Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal that removes defects without completely re-crystallizing the amophous region, ion implantation of electrically active dopant to a depth shallower than the remaining amorphous region, followed by a second anneal.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal that removes defects without completely re-crystallizing the amophous region, ion implantation of electrically active dopant to a depth shallower than the remaining amorphous region, followed by a second anneal.

Abstract: A method of forming a shallow junction in a semiconductor substrate is disclosed. The method of one embodiment comprises preamorphizing a first region of a semiconductor substrate to a first depth and implanting recrystallization inhibitors into a second region of the semiconductor substrate. The second region is a part of the first region and has a second depth. Next, a dopant is implanted into a third region of the semiconductor substrate with the third region being a part of the second region and a first annealing is performed to selectively recrystallize the first region that has no recrystallization inhibitors. Next, a second annealing is performed to recrystallize the second region and diffuse the dopant within the second region.

Abstract: A method of forming a shallow junction in a semiconductor substrate is disclosed. The method of one embodiment comprises preamorphizing a first region of a semiconductor substrate to a first depth and implanting recrystallization inhibitors into a second region of the semiconductor substrate. The second region is a part of the first region and has a second depth. Next, a dopant is implanted into a third region of the semiconductor substrate with the third region being a part of the second region and a first annealing is performed to selectively recrystallize the first region that has no recrystallization inhibitors. Next, a second annealing is performed to recrystallize the second region and diffuse the dopant within the second region.