Abstract: The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Abstract: The delay unit has first delay elements each having a first delay time and second delay elements each having a second delay time. The second delay time is greater than the first delay time. A control unit controls the delay time of the delay unit by, first, incrementally increasing or by incrementally reducing the number of second delay elements in the signal path and thereby altering the actual value of the delay in the direction towards a desired (setpoint) value until the desired value is exceeded. The control unit then, by incrementally reducing or increasing, respectively, the number of first delay elements in the signal path, alters the actual value of the delay in the direction towards the desired value until the desired value is exceeded once more. In the event of subsequent changes in the desired value or in the actual value, the number of first delay elements is incrementally altered, while the number of second delay elements in the signal path is kept constant.

Abstract: A dynamic memory includes memory cells combined to form blocks and blocks combined to form at least one block group. The memory also includes bit lines and word lines connected to the memory cells for selecting the memory cells, redundant memory cells within the blocks, at least one redundant word line in at least one of the blocks, and a decoder unit connected to the word lines. The redundant word lines are connected to the redundant memory cells for selecting the redundant memory cells. A redundant word line, after redundancy programming has been carried out, selectively replaces a word line in any of the blocks. In a first mode of operation, no more than one of the word lines is selected simultaneously per block group. In a second mode of operation, more than one of the word lines is selected simultaneously per block group, and redundancy programming is deactivated.

Abstract: An integrated circuit includes a first adjustable delay unit to which a first clock signal is fed and a second adjustable delay unit to which a second clock signal is fed. A phase detector is connected to the input and to the output of the first delay unit. A control unit serves for correcting a phase difference obtained by the phase detector and controls the delay time of the first delay unit in a corresponding manner. The control unit additionally sets the delay time of the second delay unit to essentially the same value as that of the first delay unit. Furthermore, the output of the second delay unit is connected to the input of a third adjustable delay unit.

Abstract: A circuit configuration and a method for automatic recognition and elimination of word line/bit line short circuits in a memory cell configuration containing sensor amplifiers, in which the sensor amplifiers split the memory cell configuration into memory blocks. To this end, a fuse is provided in the bit lines in each memory block upstream of the respective sensor amplifiers, the fuse being blown as a result of an appropriate voltage difference being applied in a test mode.

Abstract: A databus includes n+1 (n.gtoreq.2) lines which form n true-only lines and lead from n input blocks to n output blocks. One of the true-only lines as well as a monitoring line are associated with one of the input blocks which is located at a start of the databus and has the longest signal delay time. A NAND gate is connected downstream of the input block at the start of the databus and has an output connected to each output block.