Patents by Inventor Patrick J. Meaney

Patrick J. Meaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11088782
    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben
  • Publication number: 20210191630
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10976939
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10901839
    Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. O'Connor, Barry M. Trager, Warren E. Maule, Brad W. Michael, Marc A. Gollub, Patrick J. Meaney
  • Patent number: 10824508
    Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols for the memory modules. A host receives and decodes the ECC symbols and executes error correction operations. The host and the memory modules are coupled by a number of channels.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick J. Meaney, Christian Jacobi, Barry M. Trager
  • Patent number: 10824504
    Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. O'Connor, Jr., Barry M. Trager, Warren E. Maule, Marc A. Gollub, Brad W. Michael, Patrick J. Meaney
  • Patent number: 10747442
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10684968
    Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Cadigan, Thomas J. Dewkett, Glenn D. Gilda, Patrick J. Meaney, Craig R. Walters
  • Patent number: 10673732
    Abstract: A technique relates to dynamic time-domain reflectometry (TDR). A machine spares a bad lane in a bus. The bad lane is taken offline. TDR is dynamically executed on the bad lane while the bus is still in operation. A defect is isolated using results of the TDR.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luiz C. Alves, Patrick J. Meaney, Christopher N. Oelsner, Gary A. Peterson, Christopher Steffen
  • Patent number: 10666540
    Abstract: A technique relates to dynamic time-domain reflectometry (TDR). A machine spares a bad lane in a bus. The bad lane is taken offline. TDR is dynamically executed on the bad lane while the bus is still in operation. A defect is isolated using results of the TDR.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luiz C. Alves, Patrick J. Meaney, Christopher N. Oelsner, Gary A. Peterson, Christopher Steffen
  • Patent number: 10642535
    Abstract: A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Patrick J. Meaney, Walter Pietschmann, Nicholas Rolfe, Gary A. Van Huben
  • Publication number: 20200119843
    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben
  • Patent number: 10613951
    Abstract: Aspects of the invention include fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory. An error status of the data fetched from the primary memory is determined. The error status is one of correctable error (CE), uncorrectable error (UE), and no error. Based at least in part on determining that the data fetched from the primary memory has the error status of no error, the data fetched from the primary memory is output to the requestor. Based at least in part on determining that the data fetched from the primary memory has the error status of UE or CE, the data requested by the requestor is fetched from the secondary memory.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Gollub, Warren E. Maule, Patrick J. Meaney
  • Patent number: 10606692
    Abstract: An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, Patrick J. Meaney, James A. O'Connor, Barry M. Trager
  • Publication number: 20200097359
    Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: James A. O'Connor, Barry M. Trager, Warren E. Maule, Brad W. Michael, Marc A. Gollub, Patrick J. Meaney
  • Patent number: 10601448
    Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glenn Gilda, Patrick J. Meaney, Arthur O'Neill, Barry M. Trager
  • Publication number: 20200073565
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10558519
    Abstract: Embodiments include techniques used for a power-reduced redundant array of independent memory RAIM system. The technique includes blocking commands to one or more memory modules of the RAIM system and reading data from one or more unblocked memory modules. The technique also includes applying a power channel mark for one or more blocked memory modules, the power channel mark indicating the one or more blocked memory modules to a decoder for error correction.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glenn D. Gilda, Patrick J. Meaney
  • Publication number: 20200042205
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
    Type: Application
    Filed: October 10, 2019
    Publication date: February 6, 2020
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 10541782
    Abstract: Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben