Patents by Inventor Patrick M. Martin
Patrick M. Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10026613Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.Type: GrantFiled: August 3, 2017Date of Patent: July 17, 2018Assignee: APPLIED MATERIALS, INC.Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
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Publication number: 20170330750Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.Type: ApplicationFiled: August 3, 2017Publication date: November 16, 2017Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA, Errol Antonio C. SANCHEZ, Patrick M. MARTIN
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Patent number: 9799531Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.Type: GrantFiled: June 28, 2016Date of Patent: October 24, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
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Patent number: 9767987Abstract: A method of treating resist features comprises positioning, in a process chamber, a substrate having a set of patterned resist features on a first side of the substrate and generating a plasma in the process chamber having a plasma sheath adjacent to the first side of the substrate. The method may further comprise modifying a shape of a boundary between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the shape of the boundary is not parallel to a plane defined by a front surface of the substrate facing the plasma, wherein ions from the plasma impinge on the patterned resist features over a wide angular range during a first exposure.Type: GrantFiled: May 28, 2014Date of Patent: September 19, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Patrick M. Martin, Timothy J. Miller, Vikram Singh
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Patent number: 9716012Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.Type: GrantFiled: December 4, 2014Date of Patent: July 25, 2017Assignee: Applied Materials, Inc.Inventors: David Thompson, Huixiong Dai, Patrick M. Martin, Timothy Michaelson, Kadthala R. Narendrnath, Robert Jan Visser, Jingjing Xu, Lin Zhang
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Publication number: 20160307774Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA, Errol Antonio C. SANCHEZ, Patrick M. MARTIN
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Patent number: 9406507Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.Type: GrantFiled: March 18, 2015Date of Patent: August 2, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
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Patent number: 9340877Abstract: A method of reducing surface roughness of a resist feature disposed on a substrate includes generating a plasma having a plasma sheath and ions therein. A shape of the boundary between the plasma and plasma sheath is modified using a plasma sheath modifier, so that a portion of the boundary facing the substrate is not parallel to a plane defined by the substrate. During a first exposure, the resist feature is exposed to electromagnetic radiation having a desired wavelength and the ions are accelerated across the boundary having the modified shape toward the resist features over an angular range.Type: GrantFiled: May 7, 2013Date of Patent: May 17, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Patrick M. Martin
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Publication number: 20150311292Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.Type: ApplicationFiled: March 18, 2015Publication date: October 29, 2015Inventors: Swaminathan T. SRINIVASAN, Fareen Adeni KHAJA, Errol Antonio C. SANCHEZ, Patrick M. MARTIN
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Publication number: 20150275364Abstract: Provided are apparatus and methods for the sequential deposition and annealing of a film within a single processing chamber. An energy source positioned within the processing chamber in an area isolated from process gases can be used to rapidly form and decompose a film on the substrate without damaging underlying layers due to exceeding the thermal budget of the device being formed.Type: ApplicationFiled: March 24, 2015Publication date: October 1, 2015Inventors: David Thompson, Huixiong Dai, Patrick M. Martin, Timothy Michaelson, Kadthala R. Narendrnath, Robert Jan Visser, Jingjing Xu, Lin Zhang
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Publication number: 20150162214Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.Type: ApplicationFiled: December 4, 2014Publication date: June 11, 2015Inventors: David Thompson, Huixiong Dai, Patrick M. Martin, Timothy Michaelson, Kadthala R. Narendrnath, Robert Jan Visser, Jingjing Xu, Lin Zhang
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Patent number: 8974683Abstract: A method of reducing roughness in an opening in a surface of a resist material disposed on a substrate, comprises generating a plasma having a plasma sheath and ions therein. The method also includes modifying a shape of a boundary defined between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the boundary facing the resist material is not parallel to a plane defined by the surface of the substrate. The method also includes providing a first exposure of ions while the substrate is in a first position, the first exposure comprising ions accelerated across the boundary having the modified shape toward the resist material over an angular range with respect to the surface of the substrate.Type: GrantFiled: September 9, 2011Date of Patent: March 10, 2015Inventors: Ludovic Godet, Patrick M. Martin, Joseph C. Olson, Andrew J. Hornak
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Patent number: 8952344Abstract: A method of treating a substrate includes directing first ions over a first range of angles to one or more photoresist features disposed on the substrate, the first ions effective to generate an altered layer in the one or more photoresist features, the altered surface layer encapsulating an inner portion of the one or more photoresist features, and directing second ions different from the first ions over a second range of angles to the one or more photoresist features, the second ions effective to generate gaseous species in the inner regions of the one or more photoresist features.Type: GrantFiled: March 14, 2013Date of Patent: February 10, 2015Assignee: Varian Semiconductor Equipment AssociatesInventors: Frank Sinclair, Ludovic Godet, Patrick M. Martin, Armah Kpissay
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Patent number: 8937019Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.Type: GrantFiled: April 2, 2013Date of Patent: January 20, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Jonathan G. England, Patrick M. Martin, David Cox
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Patent number: 8912097Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.Type: GrantFiled: August 19, 2010Date of Patent: December 16, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Patrick M. Martin, Steven Carlson, Choong-Young Oh, Jung-Wook Park
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Publication number: 20140306127Abstract: A method of treating resist features comprises positioning, in a process chamber, a substrate having a set of patterned resist features on a first side of the substrate and generating a plasma in the process chamber having a plasma sheath adjacent to the first side of the substrate. The method may further comprise modifying a shape of a boundary between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the shape of the boundary is not parallel to a plane defined by a front surface of the substrate facing the plasma, wherein ions from the plasma impinge on the patterned resist features over a wide angular range during a first exposure.Type: ApplicationFiled: May 28, 2014Publication date: October 16, 2014Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, Patrick M. Martin, Timothy J. Miller, Vikram Singh
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Patent number: 8778603Abstract: A method of treating resist features comprises positioning, in a process chamber, a substrate having a set of patterned resist features on a first side of the substrate and generating a plasma in the process chamber having a plasma sheath adjacent to the first side of the substrate. The method may further comprise modifying a shape of a boundary between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the shape of the boundary is not parallel to a plane defined by a front surface of the substrate facing the plasma, wherein ions from the plasma impinge on the patterned resist features over a wide angular range during a first exposure.Type: GrantFiled: March 11, 2011Date of Patent: July 15, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Patrick M. Martin, Timothy J. Miller, Vikram Singh
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Patent number: 8698109Abstract: A computer readable storage medium containing program instructions for treating a photoresist relief feature on a substrate having an initial line roughness and an initial critical dimension, that, when executed cause a system to: direct ions toward the photoresist relief feature in a first exposure at a first angular range and at a first ion dose rate configured to reduce the initial line roughness to a second line roughness; and direct ions toward the photoresist relief feature in a second exposure at a second ion dose rate greater than the first ion dose rate, the second ion dose rate being configured to swell the photoresist relief feature.Type: GrantFiled: January 14, 2013Date of Patent: April 15, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Christopher J. Leavitt, Joseph C. Olson, Patrick M. Martin
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Publication number: 20130284697Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.Type: ApplicationFiled: April 2, 2013Publication date: October 31, 2013Inventors: Jonathan G. England, Patrick M. Martin, David Cox
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Patent number: 8460569Abstract: A method of patterning a substrate, comprises providing a set of patterned features on the substrate, exposing the set of patterned features to a dose of ions incident on the substrate over multiple angles, and selectively etching exposed portions of the patterned features.Type: GrantFiled: April 7, 2011Date of Patent: June 11, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Christopher R. Hatem, Patrick M. Martin, Timothy J. Miller