Abstract: Gate-all-around integrated circuit structures having depopulated channel structures and isolation structures are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires, the first vertical arrangement of nanowires having a dielectric structure or a conductive via in place of one or more of the nanowires, the dielectric structure having a dielectric liner and a dielectric fill. A first gate stack is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires having nanowires horizontally corresponding to the nanowires and the conductive via of the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.

Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Abstract: Gate-all-around integrated circuit structures having three-dimensional (3D) conductive contact structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires. A first epitaxial source or drain structure is at an end of the first vertical stack of horizontal nanowires. A second epitaxial source or drain structure is at an end of the second vertical stack of horizontal nanowires. The second epitaxial source or drain structure is vertically beneath the first epitaxial source or drain structure. A conductive contact structure is through the first epitaxial source or drain structure and extending only partially into the second epitaxial source or drain structure.

Abstract: Heat sink incorporation in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer. A second device layer is below the first device layer. An interconnect structure is between the first device layer and the second device layer. A heat sink material layer is between the interconnect structure and the second device layer.

Abstract: Integrated circuit structures having varied percentage-Ge silicon germanium nanowires, and methods of fabricating integrated circuit structures having varied percentage-Ge silicon germanium nanowires, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A lower one of the horizontal nanowires has a relatively higher percentage-Ge silicon and germanium composition. An upper one of the horizontal nanowires has a relatively lower percentage-Ge silicon and germanium composition. An intermediate horizontal nanowire is vertically between the lower one of the horizontal nanowires and the upper one of the horizontal nanowires and has an intermediate percentage-Ge silicon and germanium composition between the relatively higher percentage-Ge silicon and germanium composition and the relatively lower percentage-Ge silicon and germanium composition. A gate structure is vertically around the stack of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having a heterogeneous or mixed cFET architecture are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires including (110) silicon nanowires, and the second vertical stack of horizontal nanowires including (100) silicon nanowires, or the first vertical stack of horizontal nanowires including (100) silicon nanowires, and the second vertical stack of horizontal nanowires including (110) silicon nanowires. First epitaxial source or drain structures are at ends of the first vertical stack of horizontal nanowires. Second epitaxial source or drain structures are at ends of the second vertical stack of horizontal nanowires, the second epitaxial source or drain structures vertically beneath and having a different composition than the first epitaxial source or drain structures.

Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).

Abstract: Device stacking in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer above a first interconnect structure, the first device layer including nanowire-based transistors or fin-based transistors. The integrated circuit structure includes a second device layer below a second interconnect structure, the second device layer including nanowire-based transistors or fin-based transistors, and the second interconnect structure bonded directly to the first interconnect structure.

Abstract: Embodiments herein relate to a three-transistor gain cell which is provided using a complementary field-effect transistor device to achieve scaling. The cell includes an n-type layer arranged above a p-type layer. In one implementation, two nMOS transistors are arranged above one pMOS transistor and a conductive path is provided to connect the gate of one of the nMOS transistors to a storage node in the p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is arranged above two pMOS transistors and a conductive path is provided to connect the gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor.

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

Abstract: A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.

Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.

Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.

Abstract: Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.

Abstract: Techniques are provided herein to form semiconductor devices having conductive backside structures to couple various transistor structures. In some embodiments, a given conductive backside structure acts as a shunt interconnect between two transistors, such as between the gate of one transistor and the source or drain region of another transistor. In an example, an integrated circuit includes two transistor devices having semiconductor material extending between separate source and drain regions and different gate structures over or around the semiconductor material of the two transistor devices. A conductive backside structure may be formed from the backside of the integrated circuit (e.g., after removing all or most of the substrate), where the backside structure contacts the source or drain region of one transistor and the gate structure of the other transistor.

Abstract: A rotary oscillator array (ROA) apparatus includes a plurality of rotary traveling wave oscillators (RTWOs) configured to generate a plurality of resonant clock signals. An RTWO of the plurality of RTWOs includes a plurality of inverter cells and a fractional divider. The inverter cells are coupled in parallel to each other between two metal interconnects. The fractional divider is coupled to the two metal interconnects. The fractional divider will output a resonant clock signal of the plurality of resonant clock signals based on a reset-out signal generated by a reset-out terminal of the RTWO.

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.

Abstract: Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.