Patents by Inventor Patrick Morrow

Patrick Morrow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393818
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ravi Pillarisetty, Abhishek A. Sharma, Aaron D. Lilak, Willy Rachmady, Rishabh Mehandru, Kimin Jun, Anh Phan, Hui Jae Yoo, Patrick Morrow, Cheng-Ying Huang
  • Patent number: 11387238
    Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-ying Huang, Willy Rachmady, Aaron Lilak
  • Patent number: 11380684
    Abstract: Stacked transistor structures including one or more thin film transistor (TFT) material nanowire or nanoribbon channel regions and methods of forming same are disclosed. In an embodiment, a second transistor structure has a TFT material nanowire or nanoribbon stacked on a first transistor structure which also includes nanowires or nanoribbons comprising TFT material or group IV semiconductor. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. Top and bottom transistor structures (e.g., NMOS/PMOS) may be formed using the top and bottom channel region structures. An insulator region may be interposed between the upper and lower channel regions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Aaron Lilak, Cheng-Ying Huang, Jack Kavalieros, Willy Rachmady, Anh Phan, Ehren Mannebach, Abhishek Sharma, Patrick Morrow, Hui Jae Yoo
  • Patent number: 11374004
    Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Anh Phan, Gilbert Dewey, Willy Rachmady, Stephen M. Cea, Sayed Hasan, Kerryann M. Foley, Patrick Morrow, Colin D. Landon, Ehren Mannebach
  • Patent number: 11348897
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
  • Patent number: 11342227
    Abstract: One of a source, drain or gate terminal of an upper-level transistor structure is coupled to one of a source, drain or gate terminal of a lower-level transistor structure through an asymmetrical interconnect having a lateral width that increases within a dimension parallel to a semiconductor sidewall of the upper-level transistor by a greater amount than in an orthogonal dimension.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Ehren Mannebach, Nafees Kabir, Patrick Morrow, Gilbert Dewey, Willy Rachmady, Anh Phan
  • Patent number: 11328951
    Abstract: A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Rishabh Mehandru
  • Publication number: 20220140127
    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventors: Patrick MORROW, Kimin JUN, Il-Seok SON, Donald W. NELSON
  • Publication number: 20220140128
    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: Patrick MORROW, Kimin JUN, Il-Seok SON, Donald W. NELSON
  • Publication number: 20220130803
    Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: Brennen K. MUELLER, Patrick MORROW, Kimin JUN, Paul B. FISCHER, Daniel PANTUSO
  • Publication number: 20220123128
    Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side . A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Inventors: Patrick MORROW, Rishabh MEHANDRU, Aaron D. LILAK
  • Patent number: 11310325
    Abstract: A computing system may automatically infer one or more events that occur during an application session involving activity on a network, such as the Internet. Such an application session may be interactions with, for example, social networking websites, banking websites, news websites, and so on. Events are any of a number of activities or transactions that may occur during the application session. The computing system may automatically infer an event by gathering network transaction data for network transactions performed by one or more client devices of a wireless communication network. The computing system may generate a network activity signature based, at least in part, on the network transaction data and apply pattern recognition and/or machine learning to the network activity signature to infer events associated with the network activity signature.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 19, 2022
    Assignee: T-Mobile USA, Inc.
    Inventors: Rami Al-Kabra, Ruchir Sinha, Jonathan Patrick Morrow, Prem Kumar Bodiga, Ijaz Ahamed Meeran Abdul Jabbar
  • Publication number: 20220115372
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 14, 2022
    Inventors: Aaron LILAK, Patrick MORROW, Gilbert DEWEY, Willy RACHMADY, Rishabh MEHANDRU
  • Publication number: 20220102346
    Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.
    Type: Application
    Filed: December 9, 2021
    Publication date: March 31, 2022
    Inventors: Aaron D. LILAK, Rishabh MEHANDRU, Ehren MANNEBACH, Patrick MORROW, Willy RACHMADY
  • Publication number: 20220102246
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.
    Type: Application
    Filed: December 9, 2021
    Publication date: March 31, 2022
    Inventors: Aaron D. LILAK, Anh PHAN, Patrick MORROW, Stephanie A. BOJARSKI
  • Publication number: 20220069094
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Inventors: Patrick MORROW, Rishabh MEHANDRU, Aaron D. LILAK, Kimin JUN
  • Patent number: 11264405
    Abstract: Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Rishabh Mehandru, Nathan D. Jack
  • Patent number: 11264493
    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, Il-Seok Son, Donald W. Nelson
  • Patent number: 11257738
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Stephanie A. Bojarski
  • Patent number: 11257929
    Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak