Patents by Inventor Patrick Roberts

Patrick Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240422011
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for providing a digital credential. Various aspects may include receiving a request for execution of a transaction on a blockchain. Aspects may also include identifying a party that originated the request. Aspects may also include selecting an issuer of a non-transferable credential stored on the blockchain. Aspects may also include requesting receipt of the non-transferable credential from the party. Aspects may include performing a credential check based on a digitally signed statement comprising key pairs of the non-transferable credential.
    Type: Application
    Filed: October 19, 2022
    Publication date: December 19, 2024
    Inventors: Kevin Sekniqi, Emin Gün Sirer, Patrick Robert O'Grady
  • Publication number: 20240412795
    Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.
    Type: Application
    Filed: August 19, 2024
    Publication date: December 12, 2024
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Publication number: 20240386006
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for managing and indexing content in a blockchain platform. Various aspects may include receiving, at the blockchain platform, content-addressable data. Aspects may also include indexing the content-addressable data. Aspects may also include generating and serving a recommendation including the content-addressable data for one or more users based on user preferences. Aspects may also include receiving an interaction from the one or more users based on the recommendation. Aspects may include updating a state of a blockchain on the blockchain platform based on the interaction.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Inventors: Patrick Robert O'Grady, Stephen Buttolph
  • Publication number: 20240385868
    Abstract: A method for blockchain management includes receiving a first definition for a custom blockchain on a blockchain platform, the first definition including definitions for default data structures. The method further includes initializing a virtual machine and configuring the virtual machine using the first definition. The method further includes receiving a second definition for the custom blockchain, the second definition including definitions for user-defined data structures. The method further includes further configuring the virtual machine using the second definition and executing the custom blockchain on the virtual machine.
    Type: Application
    Filed: May 17, 2024
    Publication date: November 21, 2024
    Inventors: Patrick Robert O’Grady, Stephen Buttolph
  • Publication number: 20240379172
    Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 14, 2024
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Publication number: 20240370710
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for writing transactions, including smart contracts, on a blockchain platform. Various aspects may include receiving a natural language input specifying a transaction to be performed on a blockchain. Aspects may also include determining, using a machine learning (ML) model, an intent of the transaction and contextual information associated with the transaction based on the natural language input. Aspects may also include determining actions (e.g., constraints/conditions) corresponding to the natural language input transaction based on the intent and the contextual information. Aspects may also include executing the transaction on the blockchain based on the actions.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Inventors: John Morrisett, Emin Gün Sirer, Patrick Robert O’Grady
  • Patent number: 12120246
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for cross-chain communication in a blockchain platform. Various aspects may include accepting, at a first blockchain, a first transaction including a message and a message payload. Aspects may also include validating, at the first blockchain, the message by signing the message using signature keys of one or more validators in a first set of validators of the first blockchain. Aspects may also include generating an aggregate signature based on the signature keys of the one or more validators in a first set of validators. Aspects may also include submitting a second transaction on to a second blockchain, the second transaction including the message and the aggregate signature. Aspects may include validating, at the second blockchain, the second transaction based on a shared registry.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: October 15, 2024
    Assignee: Ava Labs, Inc.
    Inventors: Michael Edmond Kaplan, Stephen Buttolph, Daniel Laine, Alexander Dunn, Cameron John Schultz, Aaron Buchwald, Patrick Robert O'Grady, Bernard Wong
  • Publication number: 20240333521
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for cross-chain communication in a blockchain platform. Various aspects may include accepting, at a first blockchain, a first transaction including a message and a message payload. Aspects may also include validating, at the first blockchain, the message by signing the message using signature keys of one or more validators in a first set of validators of the first blockchain. Aspects may also include generating an aggregate signature based on the signature keys of the one or more validators in a first set of validators. Aspects may also include submitting a second transaction on to a second blockchain, the second transaction including the message and the aggregate signature. Aspects may include validating, at the second blockchain, the second transaction based on a shared registry.
    Type: Application
    Filed: March 25, 2024
    Publication date: October 3, 2024
    Inventors: Michael Edmond Kaplan, Stephen Buttolph, Daniel Laine, Alexander Dunn, Cameron John Schultz, Aaron Buchwald, Patrick Robert O'Grady, Bernard Wong
  • Publication number: 20240312530
    Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 19, 2024
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Publication number: 20240296896
    Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.
    Type: Application
    Filed: May 7, 2024
    Publication date: September 5, 2024
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Patent number: 12073899
    Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Patent number: 12049465
    Abstract: The present invention is directed to compounds of Formula I: or a pharmaceutically acceptable salt thereof, wherein the substituents A, R1, R2, R3a, R3b, R4a, R4b and n are as defined herein. The inventions also directed to pharmaceutical compositions comprising the compounds, methods of treatment using the compounds and methods of preparing the compounds.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: July 30, 2024
    Assignee: Pfizer Inc.
    Inventors: Thomas Allen Chappie, Nandini Chaturbhai Patel, Patrick Robert Verhoest, Christopher John Helal, Simone Sciabola, Erik Alphie LaChapelle, Travis T. Wager, Ramalakshmi Yegna Chandrasekaran
  • Patent number: 12046296
    Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, Abdelhakim S. Alhussien
  • Publication number: 20240241007
    Abstract: Devices, systems, and methods are provided for surface-mounted leak detection on a printed circuit board. An example leak detection device includes a first and second electrical contact with a selectively conductive material disposed therebetween. At a first electrical conductivity of the selectively conductive material, the device has a first circuit state. The selectively conductive material is configured to change from the first electrical conductivity to a second electrical conductivity in an instance in which a predetermined amount of fluid is absorbed by the selectively conductive material. At the second electrical conductivity of the selectively conductive material, the device has a second circuit state indicative of a fluid leak. Corresponding systems and methods are also provided.
    Type: Application
    Filed: January 13, 2023
    Publication date: July 18, 2024
    Applicant: NVIDIA CORPORATION
    Inventors: Anthony David Gamerman, Israel Silva Dias, Kyle Patrick Roberts, Steven Hart Penna
  • Patent number: 12011533
    Abstract: The present application provides a device (100) for transferring a fluid from a surgical site, comprising an elongate body portion (102) defining a proximal end region (106) connectable to a source of negative pressure; an elongate neck portion (104) defining a distal end region (108) of the device locatable at a surgical site; a through bore (118) extending from the distal end region to the proximal end region; and a control member (116) for selectively controlling a negative pressure at the distal end region, wherein the control member comprises a valve portion (124) configured to at least partially restrict a fluid flowing along the through bore when moved from an open position towards a closed position. A system including the device for transferring a fluid from a surgical site is also provided.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: June 18, 2024
    Assignee: SPOKE MEDICAL LIMITED
    Inventors: Neil Patrick Donnelly, Patrick Robert Axon
  • Patent number: 12009034
    Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, Abdelhakim S. Alhussien
  • Patent number: 12009040
    Abstract: A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Publication number: 20240185915
    Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.
    Type: Application
    Filed: January 4, 2024
    Publication date: June 6, 2024
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Publication number: 20240160363
    Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak
  • Patent number: D1034245
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: July 9, 2024
    Assignee: Google LLC
    Inventors: Junyong Park, Benjamin Patrick Robert Jean Riot, Irina Igorevna Kozlovskaya, Eric John Fairbanks, Brian Dennis Paschke, Cédric Eric Jean-Edouard Bernard, Jonah Avram Becker, Gregoire Ludovic Vincent Vandenbussche