Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.

Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.

Abstract: Disclosed herein is a computer-implemented method comprising aggregating PFAS remediation evaluation data for a plurality of remediation options and for a plurality of predefined criteria; graphically displaying the user modifiable chart comprising the plurality of graphical representations of the aggregated PFAS remediation evaluation data, wherein: each graphical representation depicts data points visually plotted with weights, the plurality of graphical representations for the plurality of predefined criteria are visually ordered according to a rank of the plurality of predefined criteria, and the weights are based on the rank of the plurality of predefined criteria; detecting a first user input modifying the rank of at least one predefined criterion; in accordance with the first user input, automatically updating the weights of the data points; and displaying an updated user modifiable chart comprising the plurality of graphical representations of the aggregated PFAS remediation evaluation data.

Abstract: A turbine blade, including a root, a vane including a leading edge and a trailing edge and a pressure-side wall and a suction-side wall, and including cooling vents at the trailing edge, this vane also including first and second serpentine circuits; each serpentine circuit including several ducts extending in the span direction, being connected to each other by angled portions; each serpentine circuit being supplied with air by its duct that is closest to the leading edge; and wherein the vents are supplied by the first and by the second serpentine circuit.

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for proposing blocks to be added to a blockchain. Various aspects may include performing adding block headers to a first blockchain, wherein the block headers reference a set of validators. Aspects may also include adding a temporal parameter to each block header. Aspects may also include determining, based on a block signature from a block header and from the set of validators, a proposer of candidate blocks for addition to the blockchain. Aspects may also include sampling, based on a temporal parameter, a subset of validators of the set of validators. Aspects may include increasing the proposer to a plurality of proposers from the subset of validators by an incremental quantity based on a comparison of the temporal parameter to a threshold.

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for providing an application trusted execution environment. Various aspects may include performing attestation of each application enclave of a plurality of application enclaves for a plurality of applications. Aspects may also include receiving a request from a client. Aspects may also include selecting a load balancer to forward the request to the application enclaves. Aspects may also include determining a sensitivity level of the request that is associated with a secured environment parameter. Aspects may include routing, by an enclave server of the load balancer, the request to an application enclave according to the sensitivity level for execution of an application of the plurality of applications in the application trusted execution environment.

Abstract: An apparatus, method, and system for curtailing and investigating software piracy is provided. The method includes spawning user applications on a computer without use of a file on the file system. A protected application data source is retrieved by an operating system of the computer from a server and placed into a portion of memory not accessible by at least one application. The operating system also prevents the protected application data source from being written to the file system. In this manner there is no file subject to unauthorized distribution. The protected application data may also be watermarked by ordering at least one of executable functions, function call parameters, and program data according to a license identifier so that any two versions execute the same, but carry an identifier which can be used to trace piracy to the source.

Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.

Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

Abstract: A device of integration of an electric current received on an integration node, includes an operational amplifier, an integration capacitor, and a circuit for modifying an output voltage of the operational amplifier formed by a charge transfer circuit configured to be connected on the integration node and to transfer charges into the integration capacitor. The device also includes a comparison circuit configured to trigger the modification circuit at least once during the integration duration, and a storage circuit configured to store the number of triggerings which have occurred during the integration duration. The received electric current is calculated according to the output voltage as well as to the number of triggerings multiplied by the modification of the output voltage induced by the modification circuit.

Abstract: Described herein are pharmaceutical compositions comprising 2-{5-[(3-ethoxypyridin-2-yl)oxy]pyridin-3-yl}-N-[(3S,5S)-5-fluoropiperidin-3-yl]pyrimidine-5-carboxamide, or pharmaceutically acceptable salt thereof, for treatment of liver disease and diseases related thereto. Also described are compositions comprising 2-{5-[(3-ethoxypyridin-2-yl)oxy]pyridin-3-yl}-N-[(3S,5S)-5-fluoropiperidin-3-yl]pyrimidine-5-carboxamide, or pharmaceutically acceptable salt thereof and 4-(4-(1-Isopropyl-7-oxo-1,4,6,7-tetrahydrospiro[indazole-5,4?-piperidine]-1?-carbonyl)-6-methoxypyridin-2-yl)benzoic acid, or pharmaceutically acceptable salt thereof, for treatment of liver disease and diseases related thereto.

Abstract: A system and method are provided for searching and monitoring assets available for acquisition. The method includes receiving a first signal including data associated with an acquiring entity, receiving a second signal including search data generated by the acquiring entity when interacting with at least one electronic listing service comprising searchable data associated with a plurality of assets available for acquisition, storing user profile data for the acquiring entity, the user profile data comprising at least a portion of the data associated with the acquiring entity, and at least a portion of the search data. The method also includes using the user profile data to search or monitor assets listed in the at least one electronic listing service to generate a result list of matched assets and sending a third signal including an electronic notification related to the result list, to a device associated with the acquiring entity.

Abstract: A system and method are provided for controlling visibility of elements of displayed electronic content. The method includes providing via a communications module a user interface viewable by a plurality of entity devices, and enabling via the communications module the user interface to display electronic content comprising at least one element. The method also includes determining at least one filtering criterion for controlling visibility of the at least one element of the electronic content being displayed, and concealing or modifying at least one element of the electronic content as displayed in the user interface for at least one of the plurality of entity devices, according to the at least one filtering criterion.

Abstract: An apparatus, method, and system for curtailing and investigating software piracy is provided. The method includes spawning user applications on a computer without use of a file on the file system. A protected application data source is retrieved by an operating system of the computer from a server and placed into a portion of memory not accessible by at least one application. The operating system also prevents the protected application data source from being written to the file system. In this manner there is no file subject to unauthorized distribution. The protected application data may also be watermarked by ordering at least one of executable functions, function call parameters, and program data according to a license identifier so that any two versions execute the same, but carry an identifier which can be used to trace piracy to the source.

Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.

Abstract: A memory sub-system configured to dynamically select an option to process encoded data retrieved from memory cells of a memory component, based on a prediction generated using signal and noise characteristics of memory cells storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory sub-system generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory sub-system selects an option from a plurality of options configured in the memory sub-system to process the encoded data.

Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.