Patents by Inventor Patrick Roberts

Patrick Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DETERMINE BIT ERROR COUNT BASED ON SIGNAL AND NOISE CHARACTERISTICS CENTERED AT AN OPTIMIZED READ VOLTAGE
    Publication number: 20210350872
    Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, James Fitzpatrick
  • COMPUTE AN OPTIMIZED READ VOLTAGE
    Publication number: 20210350867
    Abstract: A memory device to determine a voltage optimized to read a group of memory cells by reading the group of memory cells at a plurality of test voltages, computing bit counts at the test voltages respectively, and computing count differences in the bit counts for pairs of adjacent voltages in the test voltages. When a smallest one in the count differences is found at a side of a distribution of the count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage, based on a ratio between a first count difference and a second count difference, where the first count difference is the smallest in the count differences, and the second count difference is closest in voltage to the first count difference.
    Type: Application
    Filed: April 23, 2021
    Publication date: November 11, 2021
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • READ SOFT BITS THROUGH BOOSTED MODULATION FOLLOWING READING HARD BITS
    Publication number: 20210350857
    Abstract: A memory sub-system configured to read soft bit data by adjusting the read voltage applied to read hard bit data from memory cells. For example, in response to a read command identifying a group of memory cells, a memory device is to: read the group of memory cells using a first voltage to generate hard bit data indicating statuses of the memory cells subjected to the first voltage; change (e.g., through boosted modulation) the first voltage, currently being applied to the group of memory cells, to a second voltage and then to a third voltage; reading the group of memory cells at the second voltage and at the third voltage to generate soft bit data (e.g., via an exclusive or (XOR) of the results of reading the group of memory cells at the second voltage and at the third voltage).
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Flexible printed circuit board for head-mounted display
    Patent number: 11163167
    Abstract: A head-mounted display device is provided, including an at least partially see-through display, an electrical device, and a flexible printed circuit board (FPC) arranged on a surface of a see-through portion of the display. The FPC may include a plurality of electrical traces electrically coupled to the electrical device. Each electrical trace may be separated from at least one other electrical trace by one or more respective see-through gaps. The FPC may further include a transparent material arranged between the electrical traces in each see-through gap.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Patrick Robert Doyle, Simon Hodgson
  • Iterative read calibration enhanced according to patterns of shifts in read voltages
    Patent number: 11152073
    Abstract: A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • WEARABLE DEVICE STRAPS AND ATTACHMENT HARDWARE THEREFOR
    Publication number: 20210315329
    Abstract: Low-profile latching mechanisms and related mechanical interfaces for allowing straps and other fastening accessories for limb-wearable devices are provided. The mechanisms in question allow for a very strong, yet easily releasable, connection to be made between a strap accessory and a device housing, with very little of the mechanism being visible.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 14, 2021
    Inventors: Benjamin Patrick Robert Jean Riot, Henry Michael Lubowe, Edison Tam King Miguel, Matthew Joseph Kane, Jr-Jay Jhang, Jens Mitchell Nielsen, Cédric Eric Jean-Edouard Bernard, Chadwick John Harber, Brian Dennis Paschke, Junyong Park, Mark Woolhiser Huang
  • Self Adapting Iterative Read Calibration to Retrieve Data from Memory Cells
    Publication number: 20210311668
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: AbdelHakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • Read model of memory cells using information generated during read operations
    Patent number: 11133083
    Abstract: A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Device, method, and graphical user interface for managing authentication credentials for user accounts
    Patent number: 11120123
    Abstract: In accordance with some embodiments, a method is performed at an electronic device with a display device and one or more input devices. The method includes displaying, via the display device, a user interface that includes a new-password field. The method includes detecting, via the one or more input devices, a user input that corresponds to selection of the new-password field. In response to detecting the user input that corresponds to selection of the new-password field, the method includes displaying, on the display device, a representation of a new automatically-generated password in the new-password field and displaying, on the display device, an affordance to accept the new automatically-generated password and an affordance to decline to use the new automatically-generated password.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 14, 2021
    Assignee: Apple Inc.
    Inventors: Conrad A. Shultz, Richard J. Mondello, Reza Abbasian, Ivan Krstic, Darin Adler, Charilaos Papadopoulos, Maureen Grace Daum, Guillaume Borios, Patrick Robert Burns, Alexander David Sanciangco, Brent Michael Ledvina, Chelsea Elizabeth Pugh, Kyle Brogle, Marc J. Krochmal, Jacob Klapper, Paul Russell Knight, Connor David Graham, Shengkai Wu, I-Ting Liu, Steven Jon Falkenburg
  • Compound Feature Generation in Classification of Error Rate of Data Retrieved from Memory Cells
    Publication number: 20210271422
    Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 2, 2021
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • ADAPTIVE AND/OR ITERATIVE OPERATIONS IN EXECUTING A READ COMMAND TO RETRIEVE DATA FROM MEMORY CELLS
    Publication number: 20210271415
    Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • CLASSIFICATION OF ERROR RATE OF DATA RETRIEVED FROM MEMORY CELLS
    Publication number: 20210273650
    Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • SELF ADAPTING ITERATIVE READ CALIBRATION TO RETRIEVE DATA FROM MEMORY CELLS
    Publication number: 20210271416
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: AbdelHakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • DYNAMIC ADJUSTMENT OF DATA INTEGRITY OPERATIONS OF A MEMORY SYSTEM BASED ON ERROR RATE CLASSIFICATION
    Publication number: 20210271549
    Abstract: A memory sub-system configured to dynamically select an option to process encoded data retrieved from memory cells of a memory component, based on a prediction generated using signal and noise characteristics of memory cells storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory sub-system generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory sub-system selects an option from a plurality of options configured in the memory sub-system to process the encoded data.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Self adapting iterative read calibration to retrieve data from memory cells
    Patent number: 11086572
    Abstract: A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: AbdelHakim S. Alhussien, Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat
  • Securing means for in-tubing probe retainer
    Patent number: 11085247
    Abstract: An assembly for securing a probe retention member at a desired location within a tubular interior such as in a drill string collar. The assembly may use one or more securing members external to the retention member. In some embodiments most of the stresses from the probe retention structures of the retention member are isolated.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: August 10, 2021
    Assignee: Evolution Engineering Inc.
    Inventors: Luke Anthony Stack, Aaron William Logan, Justin Christopher Logan, Patrick Robert Derkacz, Kurtis Kenneth Lee West, Robert Andrew Harris
  • Fitness tracker
    Patent number: D927999
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 17, 2021
    Assignee: Fitbit, Inc.
    Inventors: Brian Dennis Paschke, Anthony Gerald Kern, Yidan Zhang, Jonah Avram Becker, Benjamin Patrick Robert Jean Riot, Bobin Gao, Eric John Fairbanks, Junyong Park
  • Fitness tracker
    Patent number: D928000
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 17, 2021
    Assignee: FITBIT INC.
    Inventors: Cédric Eric Jean-Edouard Bernard, Junyong Park, Eric John Fairbanks, Benjamin Patrick Robert Jean Riot, Irina Igorevna Kozlovskaya, Brian Dennis Paschke, Chadwick John Harber, Jonah Avram Becker
  • Smart watch
    Patent number: D928781
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 24, 2021
    Assignee: Fitbit, Inc.
    Inventors: Irina Igorevna Kozlovskaya, Benjamin Patrick Robert Jean Riot, Anthony Gerald Kern, Derek Jenchia Loh, Bernhard Wildner, Junyong Park, Jeffrey Andrew Fisher, Patrick James Markan
  • Body of a fitness tracker
    Patent number: D929879
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 7, 2021
    Assignee: Fitbit, Inc.
    Inventors: Brian Dennis Paschke, Anthony Gerald Kern, Yidan Zhang, Jonah Avram Becker, Benjamin Patrick Robert Jean Riot, Bobin Gao, Eric John Fairbanks, Junyong Park