Patents by Inventor Patrick Smith

Patrick Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140094004
    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 3, 2014
    Inventors: Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Patrick Smith, Fabio Zürcher
  • Publication number: 20140091909
    Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Inventors: Patrick SMITH, Criswell CHOI, James Montague CLEEVES, Vivek SUBRAMANIAN, Arvind KAMATH, Steven MOLESA
  • Patent number: 8677671
    Abstract: A planar triangular patch for cleaning firearm bores. The patch has similarly sized notches placed centrally along the edges of the patch, permitting a level of pleating as the patch is inserted into a firearm bore and wraps around a jag. The patch is made of a material design to clean and preserve the interior of a firearm bore and applies uniform pressure against the bore as it presents the face of its longest radius to the bore interior, cleaning the entire bore simultaneously.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 25, 2014
    Inventor: Shane Patrick Smith
  • Publication number: 20140049328
    Abstract: A ring oscillator timer circuit can include a plurality of electrical components arranged in a cascaded combination of delay stages connected in a closed loop chain. The timer circuit can begin oscillation a programmable number of gate delays after receiving a start signal. In some examples, the number of gate delays can be programmed to fractional values. In further examples, the ring oscillator timer circuit can include a counter having an input electrically coupled to an output of a reset component.
    Type: Application
    Filed: June 27, 2013
    Publication date: February 20, 2014
    Inventors: Patrick A. Smith, Daniel G. Knierim
  • Patent number: 8631217
    Abstract: An apparatus, system, and method are disclosed for a virtual machine backup. A name module establishes an administrative machine name for a virtual machine. A space module associates at least one administrative name space with the administrative machine name. A backup module backs up files belonging to the virtual machine using a backup proxy, wherein the files are segregated under the administrative machine name and are accessible using only a secure key belonging to the virtual machine and without using a backup proxy secure key. A mask module masks out pathname components for each backup file pathname so that the backup file pathname is equivalent to a virtual machine file pathname.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason Ferris Basler, David George Derk, Vadzim Ivanovich Piletski, James Patrick Smith
  • Publication number: 20130343535
    Abstract: A user device may display, via a graphical user interface, questions associated with a voice menu that is used by an interactive voice response (IVR) system to forward calls. The user device may obtain, via the graphical user interface, user responses to the questions. In addition, the user device may send information corresponding to the user responses to the questions to a remote device. The remote device may query the IVR system to identify a call agent, in a call center, whose profile matches the information, obtain contact information of the call agent from the IVR system, and send the contact information to the user device. Furthermore, the user device may receive the contact information from the remote device and display the contact information via the graphical user interface.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 26, 2013
    Applicant: Verizon Patent and Licensing Inc.
    Inventors: Amit Singh, Patrick Smith, Vijay Arumugam, Roopa Kotha, Fariborz Ebrahimi
  • Patent number: 8545665
    Abstract: A process for the manufacture of a decorative board, which board, on its upper surface includes a decorative layer and a wear layer of cellulose and thermosetting amino resin. A decorative layer and wear layer is applied as a surface layer on a base layer and bonded thereto by pressing under elevated temperature and pressure in a laminate press. The wear layer, the decor layer and the base layer are arranged to form a stack of layers. The stack of layers are fed into a laminate press and pressed therein under heat and pressure where at least the upper surface becomes heated. The decorative board is acquired from the laminate press whereupon a forced cooling of the decorative board is initiated in order to bring the surface temperature of the decorative board down.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: October 1, 2013
    Assignee: Pergo (Europe) AB
    Inventors: Patrick Smith, Krister Hansson, Ake Sjoberg, Roland Larsson
  • Publication number: 20130246644
    Abstract: Described herein are techniques related to a wireless enhanced projector (WEP) that is utilized by one or more devices, such as a mobile phone, a cellular phone, a Smartphone, a personal digital assistant, a tablet computer, and the like. In an implementation, the one or more devices may connect to the WEP through a server device that may be connected and/or integrated with the WEP. In this implementation, at least one of the one or more devices may be configured to be a super-user device (i.e., moderator or administrator device), while the rest of the one or more devices may be regular client devices.
    Type: Application
    Filed: September 27, 2012
    Publication date: September 19, 2013
    Inventors: Adrian Ortega Garcia, Shing Yung Lo, Lin Chun Han, Soon Yueh Shen, Sivakumar Murugesu, Ong Gee Tat, Alan Previn Teres Alexis, Andrey Larionov, Yang Su Ming, Abhijeet Ashok Kolekar, Allan Hung, Neal Patrick Smith, Tung Ean Ean, Jose Gerardo Galindo Valadez, Armando Rubio Torroella, Ivan Gomes Castellanos, Mario Barba Garcia, Soo Phing Tan, Chan Wai Phang, Ooi Ooi Aik, Ooi Ping Chuin, Tan Zheng Jing, Chai Eong Boo
  • Publication number: 20130231883
    Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.
    Type: Application
    Filed: April 12, 2013
    Publication date: September 5, 2013
    Applicant: Tektronix, Inc.
    Inventors: Patrick A. Smith, David L. Kelly, Que T. Tran, Shane A. Hazzard
  • Patent number: 8520830
    Abstract: A user device may display, via a graphical user interface, questions associated with a voice menu that is used by an interactive voice response (IVR) system to forward calls. The user device may obtain, via the graphical user interface, user responses to the questions. In addition, the user device may send information corresponding to the user responses to the questions to a remote device. The remote device may query the IVR system to identify a call agent, in a call center, whose profile matches the information, obtain contact information of the call agent from the IVR system, and send the contact information to the user device. Furthermore, the user device may receive the contact information from the remote device and display the contact information via the graphical user interface.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 27, 2013
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Amit Singh, Patrick Smith, Vijay Arumugam, Roopa Kotha, Fariborz Ebrahimi
  • Publication number: 20130189823
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Application
    Filed: March 8, 2013
    Publication date: July 25, 2013
    Inventors: Arvind KAMATH, Erik SCHER, Patrick SMITH, Aditi CHANDRA, Steven MOLESA
  • Patent number: 8484919
    Abstract: A structure to form flooring transitions having outer surfaces comprising two disparate materials. In a preferred embodiment the flooring transitions includes a T-shaped molding and at least one attachment thereto. The outer surfaces of the T-molding and attachment may be comprised of different materials, even though they may sometimes have the same pattern or décor. For example, the T-molding may have a surface of real wood or veneer and the attachment may have an outer surface of abrasion resistant foil, metal, or even a visual perception element, such as lights or reflective tape. A kit is also disclosed.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: July 16, 2013
    Assignee: Pergo (Europe) AB
    Inventors: Dan Brunedal, Patrick Smith
  • Patent number: 8471308
    Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 25, 2013
    Assignee: Kovio, Inc.
    Inventors: Vivek Subramanian, Patrick Smith
  • Patent number: 8458419
    Abstract: Systems and methods for backing up applications executing on a virtual machine are provided. The method comprises submitting a first notification to a remote computing system to prepare an application running on a virtual machine for backup, such that application data consistency is maintained during the backup process; receiving a second notification from the remote computing system, indicating that the application is prepared for backup; creating a snapshot of the virtual machine in response to the second notification; and receiving application data from the computing system to process the snapshot and complete an application-specific backup for the virtual machine.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jason Ferris Basler, David George Derk, James Patrick Smith
  • Patent number: 8446706
    Abstract: High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 21, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Criswell Choi, Patrick Smith, Erik Scher, Jiang Li
  • Patent number: 8426905
    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Arvind Kamath, Erik Scher, Patrick Smith, Aditi Chandra, Steven Molesa
  • Patent number: 8424176
    Abstract: The present invention relates to methods of making and using tunable capacitors and devices. Using the methods described, one or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: April 23, 2013
    Assignee: Kovio, Inc.
    Inventors: Patrick Smith, Zhigang Wang
  • Publication number: 20130069785
    Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.
    Type: Application
    Filed: August 20, 2012
    Publication date: March 21, 2013
    Inventors: Vivek SUBRAMANIAN, Patrick Smith, Vikram Pavate, Arvind Kamath, Criswell Choi, Aditi Chandra, James Montague Cleeves
  • Patent number: 8380440
    Abstract: A method for processing seismic data. The method may include splitting the seismic data into multiple datasets according to one or more offsets; determining a first shift amount in three or more dimensions of the seismic data between a dataset having a first offset and a dataset having a second offset, determining a second shift amount in the three or more dimensions between the dataset having the second offset and a dataset having a third offset, determining a cumulative shift amount based on a shift of the first shift amount and the second shift amount and determining a corrected dataset based on the dataset having the third offset and the cumulative shift amount.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: February 19, 2013
    Assignee: WesternGeco L.L.C.
    Inventors: Victor Aarre, Patrick Smith
  • Publication number: 20130008958
    Abstract: A payment authorized door and/or gate lock system that controls access to a given area through the processing, storage and recollection of data input through a touchscreen user interface.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 10, 2013
    Inventors: Kyle Patrick Smith, Glay Hall Smith