Patents by Inventor Patrick Variot
Patrick Variot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929337Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.Type: GrantFiled: June 7, 2021Date of Patent: March 12, 2024Assignee: Invensas LLCInventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Publication number: 20230245950Abstract: An integrated device package is disclosed. The integrated device package can include a carrier, and a cap bonded to the carrier. The carrier and the cap at least partially define a cavity that is configured to receive a coolant. The integrated device package can include an inorganic material layer disposed at least on a portion of the carrier. At least a portion of the inorganic material layer is exposed to the cavity and configured to contact the coolant. The cap can be directly bonded to the carrier without an intervening adhesive. The integrated device package can include an integrated device die that is disposed in the cavity and bonded to the carrier. The integrated device die can be directly bonded to the carrier without an intervening adhesive.Type: ApplicationFiled: January 27, 2023Publication date: August 3, 2023Inventors: Belgacem HABA, Patrick VARIOT, Rajesh KATKAR, Hong SHEN
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Publication number: 20230197559Abstract: In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and methods of forming the disclosed microelectronic devices. In some embodiments, a disclosed device may include a first integrated device die. The disclosed device may further include a thermoelectric element bonded to the first integrated device die. The disclosed device may further include a heat sink disposed over at least the thermoelectric element. The thermoelectric element may be configured to transfer heat from the first integrated device die to the heat sink. The thermoelectric element directly may be bonded to the first integrated device die without an adhesive.Type: ApplicationFiled: December 16, 2022Publication date: June 22, 2023Inventors: Belgacem Haba, Rajesh Katkar, Patrick Variot, Hong Shen
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Publication number: 20230154862Abstract: A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference (“EMI”) shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.Type: ApplicationFiled: November 12, 2021Publication date: May 18, 2023Applicant: Invensas CorporationInventors: Patrick Variot, Hong Shen
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Publication number: 20230130259Abstract: An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through one or more of the conductive routing traces of the redistribution layer.Type: ApplicationFiled: October 20, 2022Publication date: April 27, 2023Inventors: Belgacem Haba, Hong Shen, Patrick Variot, Rajesh Katkar
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Publication number: 20220139846Abstract: A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.Type: ApplicationFiled: October 25, 2021Publication date: May 5, 2022Inventors: Patrick Variot, Hong Shen
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Publication number: 20210366857Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.Type: ApplicationFiled: June 7, 2021Publication date: November 25, 2021Applicant: Invensas CorporationInventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Patent number: 11031362Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.Type: GrantFiled: January 11, 2019Date of Patent: June 8, 2021Assignee: Invensas CorporationInventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Publication number: 20190148324Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier. The conductive structure can include a base and a plurality of interconnections extending continuously away from the base toward the carrier. The microelectronic element can be positioned between at least two adjacent interconnections of the plurality of interconnections. The conductive structure may be bonded to the carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The plurality of interconnections and the microelectronic element may be encapsulated. The carrier may be removed to expose free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and bond pads of the microelectronic element may be conductively connected with terminals of the microelectronic package. The conductive structure may be patterned to form external contacts.Type: ApplicationFiled: January 11, 2019Publication date: May 16, 2019Applicant: Invensas CorporationInventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Patent number: 10181447Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.Type: GrantFiled: April 21, 2017Date of Patent: January 15, 2019Assignee: Invensas CorporationInventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Publication number: 20180308813Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.Type: ApplicationFiled: April 21, 2017Publication date: October 25, 2018Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Patent number: 8384205Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.Type: GrantFiled: July 1, 2011Date of Patent: February 26, 2013Assignee: LSI CorporationInventors: Qwai Low, Patrick Variot
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Publication number: 20120018901Abstract: A method of manufacturing a flip-chip package and a flip-chip package manufactured by such method. In one embodiment, the method includes: (1) mounting a die to a first die, (2) encapsulating the second die with a molding compound and (3) selectively ablating the molding compound based on an expected heat generation of portions of the second die to reduce a thickness of the molding compound proximate the portions.Type: ApplicationFiled: July 21, 2010Publication date: January 26, 2012Applicant: LSI CorporationInventors: Patrick Variot, Qwai Low, Zafer Kutlu
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Publication number: 20110260324Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: LSI CorporationInventors: Qwai Low, Patrick Variot
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Patent number: 7993981Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.Type: GrantFiled: June 11, 2009Date of Patent: August 9, 2011Assignee: LSI CorporationInventors: Qwai Low, Patrick Variot
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Publication number: 20100314747Abstract: A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.Type: ApplicationFiled: June 11, 2009Publication date: December 16, 2010Applicant: LSI CorporationInventors: Qwai Low, Patrick Variot
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Patent number: 6492253Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.Type: GrantFiled: January 4, 2000Date of Patent: December 10, 2002Assignee: LSI Logic CorporationInventors: Chok J. Chia, Seng-Sooi Lim, Patrick Variot
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Patent number: 6489571Abstract: A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.Type: GrantFiled: October 31, 2000Date of Patent: December 3, 2002Assignee: LSI Logic CorporationInventors: Chok J. Chia, Qwai H. Low, Patrick Variot
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Patent number: 6297550Abstract: A semiconductor package (100) includes a bondable aluminum heatspreader (130) made from anodized aluminum, thereby forming an anodization layer (132) on the surface of the heatspreader. Portions of the anodization layer are removed, e.g., by grinding, in order to provide an attachment area (124) to which a wire (122) or beam may be bonded in order to electrically connect the heatspreader to a desired voltage potential, such as a ground potential or a positive or negative potential. The heatspreader is thermally bonded to a semiconductor die (102) housed within the package. The anodized aluminum heatspreader thus not only removes and dissipates heat from the semiconductor die, but also functions as a voltage or ground plane within the semiconductor package.Type: GrantFiled: April 1, 1998Date of Patent: October 2, 2001Assignee: LSI Logic CorporationInventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
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Patent number: 6143586Abstract: An electrostatic protected integrated circuit (IC) substrate and a method of making an integrated circuit package with the electrostatic protected IC substrate includes an IC substrate, having a plurality of electrical traces formed on the top of the IC substrate with the electrical traces extending from an IC chip mounting area near the center to the periphery of the IC substrate. Electrically shorting the electrical traces together with a conductive material such as conductive tape or epoxy, thereby, protecting the IC substrate against the accumulation of static charges during the assembly of the IC chip on the IC substrate. The IC chip is mounted in the mounting area on the IC substrate and the conductive material is removed before final testing.Type: GrantFiled: June 15, 1998Date of Patent: November 7, 2000Assignee: LSI Logic CorporationInventors: Chok J. Chia, Patrick Variot, Qwai H. Low