Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Abstract: Some embodiments of the invention provide a novel hash table storage that stores smaller portions of the search keys (called reduced search keys), which, in turn allows the storage to have a smaller size and/or to store more search keys. The stored portions of search keys (i.e., the reduced search keys) can be smaller than the search keys because the hash table storage uses the non-stored portions of the search keys to ensure that one storage location cannot be used for two search keys that have the same stored portions but different non-stored portions. For instance, in some embodiments, the storage stores W minus B bits of a search key, where W is the size of the search key and B is the number of search-key bits that the storage uses to ensure that the same storage location is not identified for two search keys that have the same W-B stored bits but different B bits.

Abstract: A network switch includes a plurality of ports, a parser coupled to the plurality of ports, and a processor coupled to the ports and configured to process a received packet via one of the ports. The received packet includes a first header field, a second header field, and a destination header field, each of the first, second, and destination header fields including a TTL field. The parser is configured to decide a valid bit for each of the first header field, the second header field and the destination header field, based on an availability for each of the first header field, the second header field and the destination header field. The processor is configured to execute an instruction to cause content of a select one of the first or second header field's TTL field to be copied to the destination header field.

Abstract: An embodiment includes a plurality of tables in a hardware network for performing packet processing. Each table in the plurality of tables includes a table declaration. The table declaration includes a first set of fields used for input matching and a second set of fields used as inputs for action processing. A first table is selected from the plurality of tables. Successor tables to the first table are selected from the plurality of tables. There is a third set of fields for each successor table of the successor tables. The contents of the third set of fields are output fields where the output fields are modified by the first table when a next table of the first table is the successor table of the first table.

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Abstract: An embodiment of the invention includes a plurality of tables in a hardware network for performing packet processing. Each table in the plurality of tables includes a table declaration. The table declaration includes a first set of fields used for input matching and a second set of fields used as inputs for action processing. A first table is selected from the plurality of tables. Successor tables to the first table are selected from the plurality of tables. There is a third set of fields for each successor table of the successor tables. The contents of the third set of fields are output fields where the output fields are modified by the first table when a next table of the first table is the successor table of the first table.

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract: An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of match entries. Each TCAM block is ranked in priority order. The TCAM also includes a group of TCAM headpointers. There is a TCAM headpointer coupled to each TCAM block. The TCAM headpointer indicates the highest priority match in the group of match entries in a TCAM block. The match entries within a TCAM block are prioritized in circular priority order starting from the highest priority match.

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract: A network switch includes a plurality of ports, a parser coupled to the plurality of ports, and a processor coupled to the ports and configured to process a received packet via one of the ports. The received packet includes a first header field, a second header field, and a destination header field, each of the first, second, and destination header fields including a TTL field. The parser is configured to decide a valid bit for each of the first header field, the second header field and the destination header field, based on an availability for each of the first header field, the second header field and the destination header field. The processor is configured to execute an instruction to cause content of a select one of the first or second header field's TTL field to be copied to the destination header field.

Abstract: In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.

Abstract: In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract: An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of match entries. Each TCAM block is ranked in priority order. The TCAM also includes a group of TCAM headpointers. There is a TCAM headpointer coupled to each TCAM block. The TCAM headpointer indicates the highest priority match in the group of match entries in a TCAM block. The match entries within a TCAM block are prioritized in circular priority order starting from the highest priority match.