Patents by Inventor Patrick W. Tandy

Patrick W. Tandy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6660558
    Abstract: A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, David L. Peters, Patrick W. Tandy, Chad A. Cobbley
  • Patent number: 6658727
    Abstract: A method of assembling a multi-chip module does not necessitate more the one pass through a die attach machine. The method involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6657288
    Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: December 2, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Publication number: 20030205807
    Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.
    Type: Application
    Filed: April 23, 2003
    Publication date: November 6, 2003
    Inventors: Brad D. Rumsey, Patrick W. Tandy, Willam J. Reeder, Stephen F. Moxham, Steven G. Thummel, Dana A. Stoddard, Joseph C. Young
  • Publication number: 20030193089
    Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 16, 2003
    Inventors: Brad D. Rumsey, Patrick W. Tandy, Willam J. Reeder, Stephen F. Moxham, Steven G. Thummel, Dana A. Stoddard, Joseph C. Young
  • Publication number: 20030129951
    Abstract: Microelectronic devices, methods of operating microelectronic devices, and methods of providing microelectronic devices are described. In one embodiment, a microelectronic device includes a microelectronic package which provides a housing within which integrated circuitry is received. An integrated circuit die is received within the microelectronic package and includes integrated circuitry formed thereon. The integrated circuitry comprises first transmit/receive circuitry configured to transmit and receive radio frequency signals. Second transmit/receive circuitry is provided, discrete from the first transmit/receive circuitry, and is contained within the microelectronic package. The second circuitry is configured to transmit and receive radio frequency signals, wherein the first and second transmit/receive circuitry are configured to establish wireless communication between one another within the microelectronic package.
    Type: Application
    Filed: February 19, 2003
    Publication date: July 10, 2003
    Inventor: Patrick W. Tandy
  • Publication number: 20030129271
    Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.
    Type: Application
    Filed: February 18, 2003
    Publication date: July 10, 2003
    Inventor: Patrick W. Tandy
  • Patent number: 6577004
    Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: June 10, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Patrick W. Tandy, William J. Reeder, Stephen F. Moxham, Steven G. Thummel, Dana A. Stoddard, Joseph C. Young
  • Publication number: 20030101583
    Abstract: A technique for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The technique involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine. In some embodiments, the larger die is affixed to the support structure first and in other embodiments, the smaller die is affixed to the larger die first.
    Type: Application
    Filed: January 3, 2003
    Publication date: June 5, 2003
    Inventor: Patrick W. Tandy
  • Patent number: 6553658
    Abstract: A method for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The method involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: April 29, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6542720
    Abstract: Microelectronic devices, methods of operating microelectronic devices, and methods of providing microelectronic devices are described. In one embodiment, a microelectronic device includes a microelectronic package which provides a housing within which integrated circuitry is received. An integrated circuit die is received within the microelectronic package and includes integrated circuitry formed thereon. The integrated circuitry comprises first transmit/receive circuitry configured to transmit and receive radio frequency signals.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: April 1, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6537051
    Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: March 25, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6521980
    Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: February 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Patrick W. Tandy, Joseph M. Brand, Brad D. Rumsey, Steven R. Stephenson, David J. Corisis, Todd O. Bolken, Edward A. Schrock, Brenton L. Dickey
  • Publication number: 20030001246
    Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.
    Type: Application
    Filed: August 16, 2002
    Publication date: January 2, 2003
    Inventor: Patrick W. Tandy
  • Patent number: 6499213
    Abstract: A technique for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The technique involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine. In some embodiments, the larger die is affixed to the support structure first and in other embodiments, the smaller die is affixed to the larger die first.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: December 31, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Publication number: 20020189851
    Abstract: Methods, memory devices, module boards and systems are disclosed utilizing a non-continuous conductive layer in their circuit board as opposed to a substrate having a continuous length of metal such as copper from one end to the other. By ensuring that a non-continuous conductive layer is no longer present in a substrate, deformation and warping of the substrate or circuit board can be reduced. This can reduce or prevent future errors in processing from occurring due to the tight tolerance required in processing of circuit boards.
    Type: Application
    Filed: August 1, 2002
    Publication date: December 19, 2002
    Inventor: Patrick W. Tandy
  • Patent number: 6486539
    Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: November 26, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6429385
    Abstract: Methods, memory devices, module boards and systems are disclosed utilizing a non-continuous conductive layer in their circuit board as opposed to a substrate having a continuous length of metal such as copper from one end to the other. By ensuring that a non-continuous conductive layer is no longer present in a substrate, deformation and warping of the substrate or circuit board can be reduced. This can reduce or prevent future errors in processing from occurring due to the tight tolerance required in processing of circuit boards.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: August 6, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6403457
    Abstract: Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for the wire bonding process. In general, gold coatings are desirable on electrical contact surfaces to prevent oxidation. However, the thickness of gold which is necessary on solder ball bond pads may be less and excessive gold may be disadvantageous. Thus, by masking the solder ball bond pads during the gold coating of the wire bond bond pads, a differential gold thickness may be achieved which is more advantageous for each application.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: June 11, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 6404216
    Abstract: A semiconductor leadframe with an improved test contact is disclosed. Leadframes that are coated with a harder thinner material such as Nickel/Palladium and subsequently plated with a softer and thicker metal test contact, such as gold or silver, is disclosed. The areas that are plated with the test contact are on lead fingers where a test probe would normally contact. The test probe penetrates the softer material much easier allowing for a good contact, thus better testing and burning-in.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: June 11, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy