Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: A method and apparatus is provided to identify defective laminate objects or package substrates having mounting sites for integrated circuit dies during the package substrate fabrication process. A hole is drilled or punched within the boundary of an individual package substrate contained within a larger laminate substrate and covered with a material layer coating composed of an opaque material such as a resist. The coating may then be selectively applied or removed at a later point during the fabrication process dependent upon whether the package substrate has been classified as defective or non-defective. After specific package substrates have been marked as defective, a light source and light collector are supplied to the fabrication process on opposite sides of the wafer. By shining the light source on the laminate substrate, defective package substrates can be identified by the passage of light through the hole which is no longer covered with resist.

Abstract: A method and apparatus is provided to identify defective laminate objects or package substrates having mounting sites for integrated circuit dies during the package substrate fabrication process. A hole is drilled or punched within the boundary of an individual package substrate contained within a larger laminate substrate and covered with a material layer coating composed of an opaque material such as a resist. The coating may then be selectively applied or removed at a later point during the fabrication process dependent upon whether the package substrate has been classified as defective or non-defective. After specific package substrates have been marked as defective, a light source and light collector are supplied to the fabrication process on opposite sides of the wafer. By shining the light source on the laminate substrate, defective package substrates can be identified by the passage of light through the hole which is no longer covered with resist.

Abstract: Methods, memory devices, module boards and systems are disclosed utilizing a non-continuous conductive layer in their circuit board as opposed to a substrate having a continuous length of metal such as copper from one end to the other. By ensuring that a non-continuous conductive layer is no longer present in a substrate, deformation and warping of the substrate or circuit board can be reduced. This can reduce or prevent future errors in processing from occurring due to the tight tolerance required in processing of circuit boards.

Abstract: A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: A technique for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The technique involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine. In some embodiments, the larger die is affixed to the support structure first and in other embodiments, the smaller die is affixed to the larger die first.

Abstract: A technique for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The technique involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine. In some embodiments, the larger die is affixed to the support structure first and in other embodiments, the smaller die is affixed to the larger die first.

Abstract: Solder ball bond pads and wire bond pads may be selectively coated so that the wire bond bond pads have a thicker gold coating than the solder ball bond pads. This may reduce the embrittlement of solder ball joints while providing a sufficient thickness of gold for the wire bonding process. In general, gold coatings are desirable on electrical contact surfaces to prevent oxidation. However, the thickness of gold which is necessary on solder ball bond pads may be less and excessive gold may be disadvantageous. Thus, by masking the solder ball bond pads during the gold coating of the wire bond bond pads, a differential gold thickness may be achieved which is more advantageous for each application.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: A technique for assembling a multi-chip module does not necessitate more than one pass through a die attach machine. The technique involves attaching a smaller die to a larger die without using a die attach machine. The larger die may be attached to a support structure using a die attach machine. In some embodiments, the larger die is affixed to the support structure first and in other embodiments, the smaller die is affixed to the larger die first.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.