Abstract: A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device.

Abstract: Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled multiple times. Random sampling techniques are used to sample each of the channels. One random sampling technique randomizes a starting channel in each sampling cycle. Another random sampling technique randomizes the selection of all channels in each sampling cycle. Yet another random sampling technique randomizes the sampling cycle delay period between each sampling cycle. Still another random sampling technique randomizes the channel delay period between sampling each channel.

Abstract: Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers.

Abstract: A clock and data recovery (CDR) circuit employing zero-crossing linearizing (ZCL) technique. The circuit including a voltage controlled oscillator (VCO), an inject-locked divider (ILD), a variable delay unit, a linearized loop, a bang-bang loop, and a loop filter (LP). The differential clock generated by VCO passes through ILD for frequency dividing and variable delay unit to generate 8-phase clocks. Then using these clocks, the PDs over-sample the input data, followed by synchronization and logic operation to control the CPs output current pulses. These currents filtered by LP control the VCO to finish the loop. The circuit recovers 4 channel data and corresponding clocks of the input with low power broken-down and preferable jitter performance and locking property.

Abstract: A clock and data recovery (CDR) circuit employing zero-crossing linearizing (ZCL) technique. The circuit including a voltage controlled oscillator (VCO), an inject-locked divider (ILD), a variable delay unit, a linearized loop, a bang-bang loop, and a loop filter (LP). The differential clock generated by VCO passes through ILD for frequency dividing and variable delay unit to generate 8-phase clocks. Then using these clocks, the PDs over-sample the input data, followed by synchronization and logic operation to control the CPs output current pulses. These currents filtered by LP control the VCO to finish the loop. The circuit recovers 4 channel data and corresponding clocks of the input with low power broken-down and preferable jitter performance and locking property.

Abstract: Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers.

Abstract: A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.

Abstract: A system for characterizing interruption defect induced efficiency loss in a photovoltaic cell includes an inspection system configured to acquire inspection data from a photovoltaic cell, a control system configured to: receive the inspection data acquired from the photovoltaic cell, identify one or more interruption defects in one or more fingers of an electrode of the one photovoltaic cell utilizing the inspection data, determine a spatial parameter associated with at least one of the identified interruption defects and one or more floating finger portions of the one or more fingers created by two or more identified interruption defects, determine an interruption-defect-induced efficiency loss of the photovoltaic cell based on the determined spatial parameter associated with the at least one of the identified interruption defects and the floating finger portions of the one or more fingers created by two or more identified interruption defects.

Abstract: A system and method is provided which generates integrated circuits for integrated circuits that are portable from process to process. Information generated from an integrated circuit manufactured on a first process is utilized in combination with the parameters of a subsequent manufacturing process to obtain an integrated circuit based upon that second manufacturing process. Through this system and method a particular integrated circuit design is portable from process to process.

Abstract: An improved output driver circuit is disclosed which can be utilized when a plurality of voltage potentials are present. The output driver circuit comprises a first pull-up transistor coupled to a first voltage potential, a second pull-down transistor coupled to a second voltage potential, and a pad member coupled to the first pull-up and second pull-down transistor. The driver circuit further includes a circuit means which is coupled to the pad member and the first pull-up transistor. Accordingly, through this arrangement, the circuit substantially reduces the leakage through the first pull-up transistor when the pad member is coupled to a third voltage potential. An output driver circuit in accordance with the present invention, can be utilized in an integrated circuit environment where multiple voltages such as 3.3 volts and 5 volts are present and the output driver circuit will operate effectively because the leakage path normally associated with such circuits is substantially minimized.

Abstract: A cell architecture for mixed signal applications is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a transistor arrangement in which substrate taps are located adjacent to the transistor pairs. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The cell architecture includes a substrate tap area that allows for the accommodation of a plurality of electrically isolated metal lines.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The architecture further includes a plurality of probe lines that are located within the architecture to facilitate testability of the outputs of the architecture.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract: An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract: An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy.

Abstract: A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of only two gate delays and requiring a total of only nine transistors. Another embodiment of this invention is a Tri-State circuit constructed utilizing a single NOR gate (84), a single inverter (83), a single N channel transistor (88), and two P channel transistors (86, 87). In this embodiment of my invention, a total of nine MOS transistors are required, and the propagation delay between the input terminal and the output terminal is equal to two gate delays.