Abstract: A CMS includes first and second cameras that respectively provide first and second fields of view. First and second displays depict at least portions of the first and second fields of view. The first and second displays respectively include a first and second brightness. First and second ambient light sensors are in proximity respectively to the first and second displays and provide a first and second light ambient signal indicative of an amount of ambient light respectively in a region of the first and second displays. A controller is in communication with the first and second displays and is in communication with the first and second ambient light sensors. The controller adjusts one of the first and second brightnesses of one of the first and second displays based upon at least the other of the first and second ambient light signals of the other of the first and second displays.

Abstract: A vehicle battery assembly utilizing side cooling plates. This battery assembly avoids a stacked vertical battery and cooling plate or pack arrangement, optimizes tunnel (and other) space utilization, minimizes battery assembly intrusion into the passenger compartment of the associated vehicle, and allows seat position height to be as low as possible within the passenger compartment of the associated vehicle, while still allowing vertical access to the access points and electrical contacts of the battery modules within the battery assembly. Further, such battery assembly is compatible with conventional and novel cooling pipe configurations and cooling systems.

Abstract: A vehicle battery assembly utilizing side cooling plates. This battery assembly avoids a stacked vertical battery and cooling plate or pack arrangement, optimizes tunnel (and other) space utilization, minimizes battery assembly intrusion into the passenger compartment of the associated vehicle, and allows seat position height to be as low as possible within the passenger compartment of the associated vehicle, while still allowing vertical access to the access points and electrical contacts of the battery modules within the battery assembly. Further, such battery assembly is compatible with conventional and novel cooling pipe configurations and cooling systems.

Abstract: An electrical system for a vehicle having an internal combustion engine provided with a start/stop system includes a primary battery connectible to an engine starter motor, an alternator and an electrical load in parallel with one another and selectively connectible in parallel with the primary battery via a first switch, and a third source of electrical energy selectively connectible in parallel with the alternator via a second switch. A DC/DC converter may be arranged in parallel with the alternator for selectively charging the third source of electrical energy via the second switch. A secondary battery may be arranged in parallel with the alternator.

Abstract: A plug-in hybrid electric vehicle includes an internal combustion engine driving a pair of wheels on a first axle and a transmission drivingly connecting the internal combustion engine and the wheels on a first axle. An integrated starter-generator is mounted on the internal combustion engine crankshaft between said internal combustion engine and the transmission. The vehicle further includes an electric motor driving a pair of wheels on a first axle and a main battery pack connected to a further electric motor arranged to supply electric power for driving the wheels on a second axle. The electric drive means can comprise one electric motor driving the second axle via a differential, two electric motors each driving one half of the second axle or two electric wheel motors for the respective wheels on the second axle. An additional battery is connected to the integrated starter-generator for starting the engine.

Abstract: A contact arrangement is described for connecting a power supply to electrical components in a vehicle. The contact arrangement may include a first mechanical contact for connecting a first lead of the power supply to an electrical component, and a second mechanical contact for connecting a second lead of a power supply to the electrical component. The first and second mechanical contacts are configured to disconnect the power supply in the event of a collision. The first mechanical contact is configured to be arranged substantially perpendicular to the second mechanical contact in relation to a transverse plane of the vehicle.

Abstract: A contact arrangement is described for connecting a power supply to electrical components in a vehicle. The contact arrangement may include a first mechanical contact for connecting a first lead of the power supply to an electrical component, and a second mechanical contact for connecting a second lead of a power supply to the electrical component. The first and second mechanical contacts are configured to disconnect the power supply in the event of a collision. The first mechanical contact is configured to be arranged substantially perpendicular to the second mechanical contact in relation to a transverse plane of the vehicle.

Abstract: An electrical system for a vehicle having an internal combustion engine provided with a start/stop system includes a primary battery connectible to an engine starter motor, an alternator and an electrical load in parallel with one another and selectively connectible in parallel with the primary battery via a first switch, and a third source of electrical energy selectively connectible in parallel with the alternator via a second switch. A DC/DC converter may be arranged in parallel with the alternator for selectively charging the third source of electrical energy via the second switch. A secondary battery may be arranged in parallel with the alternator.

Abstract: A plug-in hybrid electric vehicle includes an internal combustion engine driving a pair of wheels on a first axle and a transmission drivingly connecting the internal combustion engine and the wheels on a first axle. An integrated starter-generator is mounted on the internal combustion engine crankshaft between said internal combustion engine and the transmission. The vehicle further includes an electric motor driving a pair of wheels on a first axle and a main battery pack connected to a further electric motor arranged to supply electric power for driving the wheels on a second axle. The electric drive means can comprise one electric motor driving the second axle via a differential, two electric motors each driving one half of the second axle or two electric wheel motors for the respective wheels on the second axle. An additional battery is connected to the integrated starter-generator for starting the engine.

Abstract: A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the present invention reduces the load on the clock and achieves reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder.

Abstract: A system and method for echo and near end cross talk (E/N) cancellation in a communications system using a pair of FIR filter ICs, wherein a first FIR filter IC filters a plurality of low amplitude E/N signals and a first portion of a plurality of data bits of a plurality of high amplitude E/N signals, and a second FIR filter IC filters a second portion of the data bits of the high amplitude E/N signals which cannot be filtered by the first FIR filter IC. The output values from the two filters are then summed to produce the E/N cancellation signal. The present invention allows for the use of lower bit-resolution, lower power consumption, and less expensive filter ICs than conventional FIR filters implemented in a single IC.

Abstract: Multiported register files used for storing coefficients in adaptive FIR are improved upon by implementing a split memory architecture that has the ability to separately control the least significant bits and the most significant bits of coefficient values that are stored in the filter. When the filter is operated to use so-called “burst mode” updating, the updating circuitry of the filter can be disabled and only the most significant bits of the coefficients are read out from the multiported register file while the least significant bits remain unchanged. This conserves power without sacrificing precision, since only certain ones of the bits of the coefficients are used in the multiplication of the sample.

Abstract: A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the present invention reduces the load on the clock and achieves reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder.

Abstract: A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the load on the clock can be reduced, thereby achieving reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder.

Abstract: Multiported register files for use in storing coefficients in adaptive FIR filters. incorporate computational ability, e.g., the ability to perform computation on coefficient values or derivatives thereof, or to control the operations performed thereon. For example, a multiported register file may incorporate an overflow/underflow detection and/or saturation unit. Also, the multiported register file may incorporate a special encoder to speed up the multiplication process, e.g., the so-called “Booth” encoder. Likewise, the multiported register file may incorporate a converter for changing the representation of the coefficients, e.g., a two's complement to sign-magnitude converter. All computation performed in the multiported register file is performed outside of the critical path of the filtering or of the coefficient updating. Using such improved multiported register files, adaptive FIR filters can be constructed which operate faster, and with lower power consumption.

Abstract: A receiver, comprising an adaptive filter, performs blind equalization using a modified form of the constant modulus algorithm (CMA). This modified form of CMA is referred to as phase compensating CMA (PC-CMA). PC-CMA includes a phase-compensating term in the tap updating algorithm of the equalizer such that convergence to a straight constellation is achieved without the need of a rotator.

Abstract: In an Asymmetric Digital Subscriber Loop (ADSL) Discrete Multi-Tone (DMT) system, a DMT receiver uses, during start-up, an automatic gain control (AGC) element and a rotator element in place of a one-tap complex finite impulse response (FIR) filter.

Abstract: A frequency detector embodying the invention includes circuitry for comparing first (e.g., a reference) and second (e.g., a recovery clock) signals having first and second frequencies, respectively, and for producing an output signal having: (a) a first condition characterized as a “dead zone” when their frequency difference is within a predetermined frequency range; (b) a second condition when the frequency of the first signal is greater than that of the second signal by the predetermined range; and (c) a third condition when the frequency of the second signal is greater than that of the first by the predetermined range. Frequency detectors embodying the invention are suitable for use in frequency tuning systems.

Abstract: Multiported register files are employed to implement the input delays necessary for finite impulse response (FIR) filter operation. A multiported register file is a memory, typically small, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register tile may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port. At least one output of each multiported register file is coupled to the input of the next stage of the FIR filter, if any. In addition, each multiported register file feeds data from one output to the multiply-add portion of its associated stage of the FIR filter.

Abstract: A capacitance multiplier network embodying the invention includes a first resistor, R1, connected between a first node and an intermediate node and a first capacitor, C1, connected between the intermediate node and a point of reference potential. A unity gain amplifier has an input connected to the intermediate node and its output is connected via a second resistor, R2, to the first node. The unity gain amplifier ensures that the voltage drop across the second resistor is equal to the voltage drop across the first resistor. The effective capacitance, Ce, of the network is equal to C1 times [R1+R2]/R2. Thus, by making R1 larger than R2, Ce is much large than the capacitance of C1. The capacitance multiplier network is well suited for use in phase locked loop circuits and enables the integration of a very dense circuit on the same IC chip.