Abstract: In systems embodying the invention a voltage responsive circuit is used to generate a number of different clock signals having the same frequency, with each clock signal being delayed relative to any other clock signal by a certain delay which is a function of the amplitude of a control voltage applied to the voltage responsive circuit. The clock signals are multiplexed to enable any one of the different clock signals to be selected and to then be compared with a reference frequency signal for producing a gradually varying control voltage which is applied to the voltage responsive circuit. The different clock signals are suited for use in applications such as clock recovery and frequency synthesizer systems, where very little jitter is desired.

Abstract: A PLL circuit that includes a sampled phase detector, a filter and a voltage-controlled oscillator (VCO) is disclosed. The sampled phase detector compares an incoming reference signal, Vref, and the output of the VCO, VO, to generate an error signal, Ierr, representing the phase difference between the reference signal, Vref, and the VCO output, VO. The error signal, Ierr, is filtered by a low pass filter and applied to the VCO to produce an output signal, VO, that tracks the phase of the reference signal, Vref. Jitter is reduced by reducing the delay between the sampled phase detector and the VCO. Delay is reduced by utilizing short current pulses, as opposed to the continuous charge-pump current produced by conventional sampled phase detectors. The sampled phase detector injects all the charge-pump current into the VCO at once, reducing the delay by up to half of a clock cycle.

Abstract: A phase locked loop (PLL) includes a programmable frequency multiplier section and a programmable divide-by-N network connected in a feedback loop between an output and an input of the frequency multiplier. The frequency multiplier section includes programmable circuitry which is programmed to vary as a function of N to render the bandwidth of the PLL independent of the divider ratio "N". The frequency multiplier includes a charge pump circuit, a filter circuit and a voltage controlled oscillator (VCO) circuit with the programmable circuitry being formed in one of these circuits to render the bandwidth of the PLL independent of the divider ratio, whereby the bandwidth is increased and the jitter at the PLL output is decreased.

Abstract: An extended frequency lock range is achieved in a phase-locked loop (PLL) circuit based on sampled phase detectors by introducing frequency feedback into the PLL circuit. At least one data sampler samples adjacent bits of incoming data, such as data bits D.sub.X and D.sub.Y, and an edge detector samples an edge, E, of the incoming data signal between the two data bits, D.sub.X and D.sub.Y. Sequence values "101" or "010" for the data bits D.sub.X, E and D.sub.Y, are not valid and indicate that the VCO is sampling the incoming data stream too slowly. When sequence values of "101" or "010" are measured by the sampled phase detectors, the frequency of the VCO output, V.sub.O, is known to be too low, and a constant current is preferably injected by the sampled phase detector into the PLL, until the frequency becomes too high, upon which a constant current of opposite polarity is applied.

Abstract: In systems embodying the invention X clock signals having the same frequency, with each clock signal having a different phase, are supplied to the inputs of a multiplexer whose output is connected to the input of an "integer" frequency divider circuit; where X is an integer greater than 1. The mulitplexer is controlled to selectively supply different ones of the X clock signals to the frequency divider circuit for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.

Abstract: An extended frequency lock range is achieved in a PLL circuit based on sampled phase detectors by modifying a conventional PLL circuit to utilize a biased phase detector to achieve frequency acquisition of the oscillator output signal, without the need for a lock detector. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. For a positive biased phase detector, the VCO control voltage is initialized to a value below the lock-in voltage, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.

Abstract: A system and method for training a plurality of equalizers to recognize a plurality of symbols in a received signal, the plurality of equalizers deriving intermediate symbols from the received signal as a function of at least one filter coefficient, the system including 1) a phase detection circuit that determines a phase error between at least one intermediate symbol and at least one symbol in a predetermined constellation of symbols, and 2) a coefficient modification circuit that modifies at least one filter coefficient of the plurality of equalizers as a function of the phase error to cause the at least one intermediate symbol to converge toward a symbol in the predetermined constellation of symbols as the phase error approaches zero, the intermediate symbols being substantially equal to the predetermined constellation of symbols when the phase error is equal to zero.

Abstract: A PLL circuit for selecting a clock signal from among a plurality of clock signals having different phases is disclosed. The PLL circuit includes a selector for selecting at least one of the plurality of clock signals. Duty cycle distortion is avoided by ensuring that at least one of the clock signals is always selected to drive the output of the PLL circuit, P.sub.out. In one implementation, at least two of the clock signals are selected at a given time, so that at least one of the selected signals is always driving the output during a transition from one set of selected clock signals to another set of selected clock signals. In another implementation, the selector activates a desired clock signal before deactivating the currently selected clock signal, so that at least one of the clock signals is always selected. More than two phases can be simultaneously selected, for example, if there is a large capacitive load on the output signal, P.sub.out.

Abstract: A parallel sampling receiver is disclosed that utilizes a sampled binary phase detector (SBPD) to achieve byte alignment. A parallel sampling receiver utilizes five parallel sampled phase detectors to sample incoming data and an additional edge-detecting sampled binary phase detector (SBPD) operating as a phase detector for sampling the incoming data signal between two data bits, such as data bits D.sub.4 and D.sub.5. The sampled binary phase detector (SBPD) should be either high or low if there is a binary transition from high to low between data bits D.sub.4 and D.sub.5, indicating whether the sampling is being done just before or just after the falling edge, respectively. Byte alignment is provided by the parallel sampling receiver.

Abstract: The amount of jitter that results in a serial receiver having a parallel architecture Can is reduced by insuring that the edges specifically introduced by the code are actually received by the phase detector. In particular, the code is designed to increase the probability that the edges it introduces are actually received by the phase detector. In a preferred embodiment of the invention, all the edges introduced by the code are actually received by the phase detector. This is achieved by guaranteeing that the edges introduced by the code are evenly spaced in the data stream at a rate corresponding to the phase detector sampling rate. For example, if the receiver consists of N data samplers, e.g., N=5, and one phase detector, the edges introduced by the code are arranged to be N symbols apart. This may be done by inserting as the Nth symbol an overall symbol that has a dummy component so that an edge results between the N-1 symbol and the overall Nth symbol.

Abstract: A method and circuit for timing and carrier recovery of a digital signal in broadband communications systems. The digital signal is sampled at a given rate and a first k number of successive samples are stored in a local memory bank. The next m-k samples are then ignored. The stored samples are then processed such that the timing and carrier are recovered therefrom within m clock cycles. In one method for processing the stored k samples, the samples are filtered and locked so that the timing and carrier can be recovered therefrom.

Abstract: For certain high-speed applications, where high-precision is not required analog-to-digital conversion may be performed by employing several comparators, each having their own offset. Each such comparator with an offset may be constructed by employing a differential amplifier with an offset followed by a conventional comparator. Advantageously, the time to obtain a conversion to digital of an analog sample is reduced in comparison to prior art converters, thus enabling high-speed operation.

Abstract: In a digital filter having tap coefficients, a gain element is employed to scale the filter output. The gain element is controlled by an error monitor element which runs an adaptive process in accordance with the invention. Such a process causes each tap coefficient value to be changed so as to reduce power consumption in the filter. On the other hand, the process ensures that the filter output maintains an acceptable signal to noise ratio (SNR), despite losing the bit precision of the filter as a result of the change of the coefficient values.

Abstract: Convergence of blind fractionally spaced equalizers is improved, and misconvergence is corrected by training the equalizers to detect convergence of one adaptive filter, copying the tap weights of the converged adaptive filter to the other adaptive filters and shifting the tap weights of the other adaptive filters according to the expected phase difference between the respective filters. In a two-dimensional orthogonal modulation scheme the converged weights of a first filter are copied to a second filter and shifted .pi./2. For the two dimensional orthogonal modulation scheme, the probability of a proper convergence can be increased by choosing initial tap weights for the two adaptive filters with a 3.pi./4 phase difference.