Abstract: A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.

Abstract: An array of memory cells that includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . and each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts and a select transistor is formed every P wordlines, wherein P is greater than N.

Abstract: A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.

Abstract: A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

Abstract: An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.

Abstract: A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a method for shielding the bitline for a precharging scheme in which the bitline line of each page buffer is charged prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging scheme increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The bitline shielding method increases the speed of response further by shielding the effects of neighboring bitlines from each other during the evaluation cycle. The shielding method includes charging different bitlines to preset voltages and then maintaining the preset voltages on a set of the bitlines over the evaluation cycle. The preset voltages are maintained on those bitlines not connected with memory elements undergoing evaluation.

Abstract: A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. The threshold voltages of the memory elements gradually increase over operating cycles due to trapping of charge in the nitride or oxide, eventually causing errors due to the increase in threshold voltage. Internal routines are necessary to characterize the change in threshold voltages and subsequently modify the comparison circuit supplying the current used to determine whether the memory elements have attained a specific threshold. The method of automatically adjusting the window of the virtual ground array increases endurance and reliability of the virtual ground array and decreases errors caused by the increased threshold voltage.

Abstract: An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

Abstract: A P-type dopant is implanted into a substrate region 94 under a select drain gate transistor field oxide region 75 at a large tilt angle .alpha., to prevent field turn-on under the select drain gate transistor field oxide region 75 in a non-volatile memory device such as a NAND flash memory device. A substrate region 114 under a select source gate transistor field oxide region 77 can also be implanted with a P-type dopant to prevent field turn-on under the region 77 if select source gates 90 and 92 are to be supplied with a voltage in operation rather than grounded. The substrate regions 94 and 114 under both the select drain gate transistor field oxide region 75 and the select source gate transistor field oxide region 77 can be implanted with the P-type dopant using a fixed-angle ion beam 120, by rotating the wafer 124 between the step of implanting one of the substrate regions and the step of implanting the other region.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is forced while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A method and circuit for sensing multi states of a NAND memory cell by applying plurality of external sensing bias current at a constant positive gate and bias voltage and detecting a cell current wherein the cell current depends upon the state of the memory cell.

Abstract: A capacitor structure which exhibits a constant capacitance at non-negative voltages is provided by erasing a P-well floating gate NMOS transistor prior to its use as a capacitor. By erasing the transistor, a negative threshold voltage is obtained, thereby turning on the transistor and placing the transistor in an inversion state where the MOS capacitance is voltage-independent. Such transistors can be utilized as capacitors, whereby one plate of the capacitor corresponds to the control gate of the transistor and the other plate corresponds to the commonly connected source, drain, P-well, and deep N-well regions of the transistor, in voltage regulator circuits or other circuits in which node stabilization is desired. As a result, the capacitance is constant even at initialization when zero volts is applied.

Abstract: A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.

Abstract: A method and an apparatus are provided for the production and supply of an erase voltage for the initial erasing operation of a floating gate transistor used as a capacitor in a voltage regulator, along with the proper electrical connection of the capacitor's control gate and commonly connected regions. In one embodiment, a capacitor erase control circuit controls a pass transistor for connecting the control gate of the floating gate capacitor to ground and another pass transistor for isolating the commonly connected source, drain and channel regions of the floating gate capacitor (the "well node") from ground. The erase control circuit simultaneously applies a capacitor erase input and a clock input to an erase voltage pass circuit to control a third pass transistor to apply an erase voltage to the well node, thereby erasing the floating gate capacitor.

Abstract: A two part high voltage check program creates a circuit simulator input file, analyzes the resulting circuit simulator output file for design rule violations, and produces a user report of all violations. The user creates a transistor file which indicates which blocks are to be checked, and optionally specifies individual transistors within the block for checking. The user creates a rule file including rule definitions for the various different types of transistors in the design. The first part generates a print file for input to a circuit simulator. The second part reads the print file, the rule file, and the simulator output file. The second part produces a transistor linked list which is linked to the rule linked list. The second part reads the simulator output file line by line and performs the high voltage electrical rule checks for each transistor for each time step. The second part produces a violation linked lists for each transistor for each violation type.

Abstract: The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

Abstract: An EEPROM NAND array has floating gate memory cells coupled in series, each having a control gate, a floating gate, a body region, and an insulating layer between the floating gate and the body region. A negative charge pump is coupled to the body region. In programming, the body region of the memory cell selected for programming is biased to a negative voltage by the negative charge pump while the control gate of the memory cell is biased to a predetermined positive voltage sufficient to induce Fowler-Nordheim tunneling from the body region into the floating gate. The present invention allows the programming voltage requirement at the control gate of a NAND EEPROM memory cell to be significantly reduced which allows for the peripheral voltage delivery circuitry in NAND EEPROM arrays to be designed for lower voltages than for conventional NAND EEPROM arrays.

Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.