Patents by Inventor Paul A. Cain
Paul A. Cain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7629261Abstract: A process for fabricating an electronic device comprising the step of patterning a metallic electrode to the electronic device by laser ablation followed by electroless plating, wherein the process of fabricating the electronic device comprises at least one other laser patterning step over the area of the metallic electrode performed after said step of patterning the metallic electrode.Type: GrantFiled: April 4, 2006Date of Patent: December 8, 2009Assignee: Plastic Logic LimitedInventor: Paul A. Cain
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Publication number: 20090298299Abstract: The present invention relates to methods of fabricating electronic devices using laser ablation and to devices fabricated thereby. Embodiments of the methods are particularly suitable for defining electrodes within thin film transistor (TFT) structures using laser ablation in a step-and-repeat mode.Type: ApplicationFiled: August 31, 2006Publication date: December 3, 2009Applicant: PLASTIC LOGIC LIMITEDInventors: Paul A. Cain, Carl Hayton
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Publication number: 20090212292Abstract: A method of fabricating an organic electronic device is provided. The organic electronic device has a structure including an upper conductive layer and an underlying layer immediately beneath said upper conducting layer and having at least one solution process able semiconducting layer. The upper conducting layer preferably has a thickness of between 10 nm and 200 nm.Type: ApplicationFiled: May 30, 2006Publication date: August 27, 2009Inventors: Carl Hayton, Thomas Meredith Brown, Paul A. Cain
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Publication number: 20090166612Abstract: This invention relates to the fabrication of electronic devices, such as thin-film transistors, in particular thin-film transistors in which patterning techniques are used for definition of electrode patterns that need to be accurately aligned with respect to underlying electrodes. The fabrication technique is applicable to various patterning techniques, such as laser ablation patterning or solution-based, direct-write printing techniques which are not capable of forming structures with a small linewidth, and/or that cannot be positioned very accurately with respect to previously deposited patterns. We thus describe self-aligned gate techniques which are applicable for both gate patterning by a subtractive technique, in particular selective laser ablation patterning, and gate patterning by an additive technique such as printing. The techniques facilitate the use of low-resolution gate patterning.Type: ApplicationFiled: March 28, 2007Publication date: July 2, 2009Inventors: Paul A. Cain, Yong-Young Noh, Henning Sirringhaus
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Publication number: 20090113291Abstract: We describe a method of displaying a document page with a predetermined size using a display device having edges defining lateral dimensions not substantially larger than said predetermined size and having a central re-writable display portion and a non-re-writable border, said document page comprising a central, foreground portion bearing one or both of text and graphics, a background having a background colour and at least one margin having said background colour, the method comprising: inputting page data defining a page for display; processing said page data to crop margins of said page such that, when displayed on said re-writable display portion, said non-re-writable border gives the appearance of said cropped margins, said processing generating cropped page data; and outputting said cropped page data for display on said re-writable display portion of said display.Type: ApplicationFiled: June 13, 2008Publication date: April 30, 2009Applicant: PLASTIC LOGIC LIMITEDInventors: Duncan Barclay, Paul A. Cain, Steven Farmer, Carl Hayton, Simon Jones, Barry Merrick, Anusha Nirmalananthan
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Publication number: 20090109185Abstract: We describe a display device for displaying an electronic document page comprising a central rewritable portion, a non-rewritable border with external lateral physical dimensions defined by the display edges, wherein said border is coloured to substantially match a background colour of said central rewritable portion such that when a foreground part of said document page is displayed on said central rewritable portion the appearance of margins of said document page is provided by said background coloured border whereby in use said displayed electronic document page appears to extend up to said display edges, and wherein the surface of the display is substantially flat over the lateral physical dimensions from the central rewritable portion across the border to the display edges.Type: ApplicationFiled: June 13, 2008Publication date: April 30, 2009Applicant: PLASTIC LOGIC LIMITEDInventors: Duncan Barclay, Steven Farmer, Carl Hayton, Simon Jones, Anusha Nirmalananthan, Paul A. Cain, Barry Merrick
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Publication number: 20080194056Abstract: A method of producing a plurality of transistors each including a source/drain electrode pair comprising a conductor material and a channel comprising semiconductor material between the source and drain electrodes of said source/drain electrode pair; the method comprising (i) forming over a substrate at least a first layer of said conductor material or a precursor thereto and a second layer of said semiconductor material or a precursor thereto; and (ii) thereafter removing selected portions of at least said first and second layers so as to define at least two adjacent source/drain electrode pairs that are unconnected to each other within said first and second layers.Type: ApplicationFiled: April 3, 2006Publication date: August 14, 2008Applicant: Plastic Logic LimitedInventors: Paul A. Cain, Carl Hayton, Anoop Menon, Thomas M. Brown
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Publication number: 20080188092Abstract: A method of producing an array of electronic devices, the method including the steps of: forming one or more first conductive elements of a first electronic device on a substrate and one or more second conductive elements of a second electronic device on said substrate; and forming a layer of channel material over the substrate and the first and second conductive elements to provide a first channel for, in use, the movement of charge carriers between conductive elements of said first electronic device and a second channel for, in use, the movement of charge carriers between conductive elements of said second electronic device; wherein the method also includes the step (a) of using an irradiative technique to decrease in a single step the conductivity of one or more selected portions of the layer of channel material in one or more regions between the first and second conductive elements.Type: ApplicationFiled: December 16, 2005Publication date: August 7, 2008Applicant: Plastic Logic LimitedInventor: Paul A. Cain
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Publication number: 20080153285Abstract: A process for fabricating an electronic device comprising the step of patterning a metallic electrode to the electronic device by laser ablation followed by electroless plating, wherein the process of fabricating the electronic device comprises at least one other laser patterning step over the area of the metallic electrode performed after said step of patterning the metallic electrode.Type: ApplicationFiled: April 4, 2006Publication date: June 26, 2008Applicant: PLASTIC LOGIC LIMITEDInventor: Paul A. Cain
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Publication number: 20070096080Abstract: A rectifying diode comprising a semiconducting layer, a first electrode, and a second electrode, wherein the width of the region of closest contact between the two electrodes is on the order of the thickness of the semiconducting layer.Type: ApplicationFiled: July 2, 2004Publication date: May 3, 2007Inventors: Paul Cain, Henning Sirringhaus, Anoop Menon, Catherine Ramsdale, Tim Werne
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Publication number: 20070040170Abstract: An electronic device including at least first and second transistors integrated together on a substrate and each including an organic semiconductor region, wherein the first and second transistors are either both n-type or both p-type but wherein one of the first and second transistors is a normally-ON transistor and the other of the first and second transistors is a normally-OFF transistor.Type: ApplicationFiled: September 10, 2004Publication date: February 22, 2007Inventors: Paul Cain, Henning Sirringhaus, Nicholas Stone, Thomas Brown
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Publication number: 20070012950Abstract: A method of producing a metal element of an electronic device on a substrate, including the steps of: forming a mixture of a material comprising metal atoms with a liquid, depositing the material from the liquid mixture onto a substrate, and then irradiating at least part of the deposited material with light to increase the electrical conductivity of the deposited material.Type: ApplicationFiled: September 2, 2004Publication date: January 18, 2007Inventors: Paul Cain, Anoop Menon, Henning Sirringhaus, James Watts, Tim Werne, Thomas Brown
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Patent number: 6950299Abstract: An electronic device including first, second and third conductor layers respectively arranged as the source, drain and gate electrodes of a field effect transistor, the third conductor layer being capacitively coupled with both the first and second conductor layers but with the second conductor layer to a greater degree than with the first conductor layer, wherein the electronic device is operable as a non-linear capacitor by applying an alternating voltage across the third conductor layer and the first conductor layer whilst leaving the second conductor layer at a floating potential.Type: GrantFiled: February 13, 2004Date of Patent: September 27, 2005Assignee: Plastic Logic LimitedInventors: Nicholas J. Stone, Paul A. Cain, Thomas M. Brown
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Publication number: 20040223288Abstract: An electronic device including first, second and third conductor layers respectively arranged as the source, drain and gate electrodes of a field effect transistor, the third conductor layer being capacitively coupled with both the first and second conductor layers but with the second conductor layer to a greater degree than with the first conductor layer, wherein the electronic device is operable as a non-linear capacitor by applying an alternating voltage across the third conductor layer and the first conductor layer whilst leaving the second conductor layer at a floating potential.Type: ApplicationFiled: February 13, 2004Publication date: November 11, 2004Applicant: PLASTIC LOGIC LIMITEDInventors: Nicholas J. Stone, Paul A. Cain, Thomas M. Brown
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Publication number: 20040175963Abstract: Production of an electronic device by solution processing by depositing fluid including a device material or a precursor thereto onto a zone of a substrate surface between at least two opposed barriers for together controlling the spread of said fluid on the substrate surface, wherein at least one of the two opposed barriers is structured so as to facilitate controlled spillage of excess fluid out of the zone to one or more selected locations. Also, production of an electronic device by solution processing by longitudinally depositing fluid containing a device material or a precursor thereto on a patterned substrate to form a plurality of spaced longitudinal channels of said device material of controlled lateral width, wherein the substrate is patterned such that at least one lateral connection between at least one pair of adjacent channels is formed at at least one selected location without the need to carry out any lateral deposition of said fluid.Type: ApplicationFiled: March 5, 2004Publication date: September 9, 2004Applicant: PLASTIC LOGIC LIMITEDInventors: Paul A. Cain, Nicholas J Stone
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Patent number: 6787794Abstract: A quantum computer comprises a pair of qubits disposed between first and second single-electron electrometers and a control gate. The qubits each comprise a molecule of ammonia caged inside a C60 molecule disposed on a substrate. The ammonia-bearing C60 molecule is positioned using a scanning probe microscope.Type: GrantFiled: December 11, 2001Date of Patent: September 7, 2004Assignee: Hitachi, Ltd.Inventors: Paul Cain, Andrew Ferguson, David Williams
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Patent number: 6635898Abstract: A quantum computer comprises a trench-isolated channel region formed in a boron-doped silicon germanium layer which has narrow channel regions which form tunnel barriers and wide channel regions which define first and second quantum dots. Tunnelling between the first and second quantum dots is controlled by a side gate and/or a surface gate. The quantum states used to represent a qubit may be defined as |an excess hole on the first quantum dot> and |an excess hole on the second quantum dot>. A Hadamard Transformation UH of an initial state may be effected by application of a pulse to the side or surface gate. The first and second tunnel quantum dots are of unequal size which helps decouple the quantum computer from the environment.Type: GrantFiled: November 19, 2001Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: David Arfon Williams, Paul Cain
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Publication number: 20030040168Abstract: A quantum computer comprises a pair of qubits disposed between first and second single-electron electrometers and a control gate. The qubits each comprise a molecule of ammonia caged inside a C60 molecule disposed on a substrate. The ammonia-bearing C60 molecule is positioned using a scanning probe microscope.Type: ApplicationFiled: December 11, 2001Publication date: February 27, 2003Inventors: Paul Cain, Andrew Ferguson, David Williams
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Publication number: 20020190249Abstract: A quantum computer comprises a trench-isolated channel region formed in a boron-doped silicon germanium layer which has narrow channel regions which form tunnel barriers and wide channel regions which define first and second quantum dots. Tunnelling between the first and second quantum dots is controlled by a side gate and/or a surface gate. The quantum states used to represent a qubit may be defined as |an excess hole on the first quantum dot> and |an excess hole on the second quantum dot>. A Hadamard Transformation UH of an initial state may be effected by application of a pulse to the side or surface gate. The first and second tunnel quantum dots are of unequal size which helps decouple the quantum computer from the environment.Type: ApplicationFiled: November 19, 2001Publication date: December 19, 2002Inventors: David Arfon Williams, Paul Cain
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Patent number: 6136525Abstract: An artificial liver support system is described herein which comprises cryopreserved hepatocytes having an initial viability of 80-99%. Further disclosed are hepatocytes cryopreserved by dispensing hepatocytes into freezing containers, freezing the containers from between minus 50 to minus 90 degrees Celsius, storing the containers in liquid or vapor nitrogen, thawing the cryopreserved hepatocytes when ready for use and removing residual cryoprotectant media.Type: GrantFiled: August 2, 1999Date of Patent: October 24, 2000Assignee: Circe Biomedical, Inc.Inventors: Claudy Jean-Paul Mullon, Shawn Paul Cain, Timothy Jon Perlman, Hugo O. Jauregui, Sharda Naik, Henry A. Santangini, Donna M. Trenkler