Patents by Inventor Paul A. Grudowski

Paul A. Grudowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9847389
    Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: December 19, 2017
    Assignee: NXP USA, Inc.
    Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
  • Patent number: 8980734
    Abstract: An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., 21, 31, 41, 51) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS 112) having switched or altered work function metal layers (82) where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tab A. Stephens, Perry H. Pelley, Michael B. McShane, Paul A. Grudowski
  • Publication number: 20140252487
    Abstract: An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., 21, 31, 41, 51) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS 112) having switched or altered work function metal layers (82) where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tab A. Stephens, Perry H. Pelley, Michael B. McShane, Paul A. Grudowski
  • Publication number: 20140054704
    Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 27, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
  • Patent number: 8569858
    Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: October 29, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
  • Patent number: 8021957
    Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 20, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Venkat R. Kolagunta, Mehul D. Shroff
  • Publication number: 20110210401
    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
  • Publication number: 20110003444
    Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Paul A. Grudowski, Venkat R. Kolagunta, Mehul D. Shroff
  • Patent number: 7843011
    Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: November 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Venkat R. Kolagunta, Mehul D. Shroff
  • Patent number: 7745298
    Abstract: A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: June 29, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tab A. Stephens, Olubunmi O. Adetutu, Paul A. Grudowski, Matthew T. Herrick
  • Patent number: 7736957
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 15, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Darren V. Goedeke, Voon-Yew Thean, Stefan Zollner
  • Patent number: 7714318
    Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: May 11, 2010
    Assignee: Freescale Semiconductor, Inc
    Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
  • Patent number: 7700499
    Abstract: A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: April 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kurt H. Junker, Paul A. Grudowski, Xiang-Zheng Bo, Tien Ying Luo
  • Patent number: 7687354
    Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
  • Patent number: 7678698
    Abstract: A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: March 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiangzheng Bo, Tien Ying Luo, Kurt H. Junker, Paul A. Grudowski, Venkat R. Kolagunta
  • Publication number: 20090221119
    Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
  • Patent number: 7579228
    Abstract: A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (210); (b) forming a first set of organic spacers (213) adjacent to said first electrode; (c) depositing a first photo mask (215) over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 25, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Kurt H. Junker, Thomas J. Kropewnicki, Andrew G. Nagy
  • Publication number: 20090142895
    Abstract: A method for forming a via includes forming a gate electrode over a semiconductor substrate, forming a source/drain region in the semiconductor substrate adjacent the gate electrode, forming a silicide region in the source/drain region, forming a post-silicide spacer adjacent the gate electrode after forming the silicide region, forming an interlayer dielectric layer over the gate electrode, the post-silicide spacer, and the silicide region, and forming a conductive via in the interlayer dielectric layer, extending to the silicide region.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventors: Tab A. Stephens, Olubunmi O. Adetutu, Paul A. Grudowski, Matthew T. Herrick
  • Patent number: 7538002
    Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: May 26, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Vance H. Adams, Bich-Yen Nguyen, Paul A. Grudowski
  • Patent number: 7528029
    Abstract: A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Darren V. Goedekc, John J. Hackenberg