Patents by Inventor Paul A. Merolla

Paul A. Merolla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FINAL FAULTY CORE RECOVERY MECHANISMS FOR A TWO-DIMENSIONAL NETWORK ON A PROCESSOR ARRAY
    Publication number: 20140095923
    Abstract: Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, JR., Andrew S. Cassidy, Subramanian Iyer, Paul A. Merolla, Dharmendra S. Modha
  • Integrate and fire electronic neurons
    Patent number: 8473439
    Abstract: An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, Gregory S. Corrado, Steven K. Esser, Paul A. Merolla, Dharmendra S. Modha
  • NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALABLE NEURAL NETWORK
    Publication number: 20130073497
    Abstract: An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicants: Cornell University, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Filipp Akopyan, John V. Arthur, Rajit Manohar, Paul A. Merolla, Dharmendra S. Modha, Alyosha Molnar, William P. Risk, III
  • INTEGRATE AND FIRE ELECTRONIC NEURONS
    Publication number: 20120150781
    Abstract: An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 14, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES, INC.
    Inventors: John V. Arthur, Gregory S. Corrado, Steven K. Esser, Paul A. Merolla, Dharmendra S. Modha