Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

Abstract: Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: An integrated circuit structure includes an active region containing more active semiconductor devices, wherein the active region comprises a first grating of metal and dielectric materials with only vertically aligned structures thereon. A transition region containing inactive structures is adjacent to the active region, wherein the transition region comprises a second grating of metal and dielectric materials having at least one of vertical aligned structures and vertical random structures thereon. Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, a method of fabricating a semiconductor device comprises, forming a first grating of parallel first lines, forming a second grating of parallel second lines, wherein the second lines are substantially orthogonal to the first lines, and wherein the first lines and second lines define a plurality of first openings, disposing a conformal mask layer over the first lines and the second lines, wherein the conformal mask layer partially fills the first openings and defines a second opening within each of the first openings, disposing a hardmask over the conformal mask layer, wherein the hardmask fills the second openings, patterning third openings into the hardmask, wherein the third openings clear the hardmask from at least one of the second openings, and removing the mask layer proximate to cleared second openings to clear first openings.

Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.

Abstract: A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, a structure for directed self-assembly includes a substrate and a block co-polymer structure disposed above the substrate. The block co-polymer structure has a polystyrene (PS) component and a polymethyl methacrylate (PMMA) component. One of the PS component or the PMMA component is photosensitive.

Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.

Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.