Patents by Inventor Paul A. Ronsheim

Paul A. Ronsheim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6329704
    Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: December 11, 2001
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim
  • Publication number: 20010030333
    Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.
    Type: Application
    Filed: June 6, 2001
    Publication date: October 18, 2001
    Inventors: Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim
  • Patent number: 6194736
    Abstract: Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of quantum conductive recrystallization barrier layers. The quantum conductive layers are preferably used in trench capacitors to act as recrystallization barriers.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: February 27, 2001
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Susan E. Chaloux, Tze-Chiang Chen, Johnathan E. Faltermeier, Ulrike Gruening, Rajarao Jammy, Jack A. Mandelman, Christopher C. Parks, Paul C. Parries, Paul A. Ronsheim, Yun-Yu Wang
  • Patent number: 6114257
    Abstract: A process for thermal oxidation of a semiconductor substrate comprising exposing the substrate to a chlorine plasma, and then heating the substrate in an oxidizing ambient. The substrate may comprise silicon, germanium, or a combination thereof. The heating step may further comprise heating at a temperature of between about 750.degree. C. and about 850.degree. C.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventor: Paul A. Ronsheim
  • Patent number: 5656514
    Abstract: A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: August 12, 1997
    Assignee: International Business Machines Corporation
    Inventors: David Ahlgren, Jack Chu, Martin Revitz, Paul Ronsheim, Mary Saccamango, David Sunderland
  • Patent number: 5385850
    Abstract: A low temperature, epitaxial, in situ doped semiconductor layer is used as a sacrificial dopant source. The resulting doped region is small-dimensioned with a tightly controlled dopant concentration. The dopant layer is oxidized in a relatively low-temperature environment, and removed by etching. The process can be used to form a vertical bipolar transistor, where the doped region is the base, and wherein portions of the oxidized dopant layer are left as insulators.
    Type: Grant
    Filed: February 7, 1991
    Date of Patent: January 31, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Chang-Ming Hsieh, Victor R. Nastasi, Martin Revitz, Paul A. Ronsheim
  • Patent number: 5194397
    Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: March 16, 1993
    Assignee: International Business Machines Corporation
    Inventors: Robert K. Cook, Ronald W. Knepper, Subodh K. Kulkarni, Russell C. Lange, Paul A. Ronsheim, Seshadri Subbanna, Manu J. Tejwani, Bob H. Yun