Abstract: An artifact free inert filter medium for collection of organic particles is a fibrous material is developed that can be formed into filters used in ambient and indoor air sampling equipment for subsequent laboratory chemical analysis by one of several thermal optical or thermal analysis methods for the determination of organic carbon (OC), elemental carbon (EC), pyrolysis carbon (PC), and total carbon (TC, sum of OC+EC), carbon fractions determined by thermal or thermal-optical analysis methods (OC1, OC2, OC3, OC4, PC, EC1, EC2, EC3) as well can be analyzed in the laboratory for individual organic species by a range of thermal analysis and or extraction/analysis methods.

Abstract: A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

Abstract: A multi-filter chemical speciation sampler and a virtual impaction particle separation inlet therefore are provided. The inlet includes a housing having a bottom, a collection tube that extends through the bottom, and collection apertures formed in the bottom, arranged around the collection tube; a first plate disposed on top of the housing, having acceleration nozzles disposed at the perimeter thereof; a second plate disposed in the housing below the first plate, having a central aperture and separation apertures disposed around the central aperture. The sampler includes: an inlet; a virtual impaction separator to further fractionate the PM into a course fraction and a fine fraction; a first separation assembly to divide the course fraction into coarse aliquots, comprising first filters to collect the coarse aliquots; a second separation assembly to divide the fine fraction into fine aliquots, comprising second filters to collect the fine aliquots.

Abstract: A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

Abstract: A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.

Abstract: A Schottky field effect transistor (FET) includes a gate stack located on a silicon on insulator (SOI) layer, the gate stack comprising a gate silicide region; and source/drain silicide regions located in the SOI layer, the source/drain silicide regions comprising and at least one of sulfur and fluorine, wherein an interface comprising arsenic is located between each of the source/drain silicide regions and the SOI layer. A method of forming a contact, the contact comprising a silicide region adjacent to a silicon region, includes co-implanting the silicide region with arsenic and at least one of sulfur and fluorine; and drive-in annealing the co-implanted silicide region to diffuse the arsenic to an interface between the silicide region and the silicon region.

Abstract: A multi-filter chemical speciation sampler and a virtual impaction particle separation inlet therefore are provided. The inlet includes a housing having a bottom, a collection tube that extends through the bottom, and collection apertures formed in the bottom, arranged around the collection tube; a first plate disposed on top of the housing, having acceleration nozzles disposed at the perimeter thereof; a second plate disposed in the housing below the first plate, having a central aperture and separation apertures disposed around the central aperture. The sampler includes: an inlet; a virtual impaction separator to further fractionate the PM into a course fraction and a fine fraction; a first separation assembly to divide the course fraction into coarse aliquots, comprising first filters to collect the coarse aliquots; a second separation assembly to divide the fine fraction into fine aliquots, comprising second filters to collect the fine aliquots.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: An apparatus for sampling ambient air to obtain coarse and fine fractions of particulate matter includes a single acceleration tube and a collection tube coaxially arranged along a central axis with a gap between facing distal ends thereof within a range of d/D1 of 1 to 2, wherein d is the distance or gap between the distal ends and D1 is the inside diameter of the outlet at the distal end of the acceleration tube. A housing surrounding the acceleration and concentration tubes is provided with a side-wall nozzle connected to a suction device for drawing a major portion of the sampled ambient air therethrough and for separation of particulate matter, as a fine fraction, from that major portion.

Abstract: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.

Abstract: A method of creating ultra thin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.

Abstract: An apparatus for sampling ambient air to obtain coarse and fine fractions of particulate matter includes a single acceleration tube and a collection tube coaxially arranged along a central axis with a gap between facing distal ends thereof within a range of d/D1 of 1 to 2, wherein d is the distance or gap between the distal ends and D1 is the inside diameter of the outlet at the distal end of the acceleration tube. A housing surrounding the acceleration and concentration tubes is provided with a side-wall nozzle connected to a suction device for drawing a major portion of the sampled ambient air therethrough and for separation of particulate matter, as a fine fraction, from that major portion.

Abstract: A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.

Abstract: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

Abstract: A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device.

Abstract: A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.