Abstract: An electrical connector can include a male blade terminal protector that protects one or more male blade terminals from external objects before, during, and after coupling of the male connector to a female connector. The male blade terminal protector can be slidably disposed within a housing of the male connector and configured to retract when the female connector is coupled to the male connector and extend when the female connector is decoupled from the male connector. The male blade terminal protector is moveable from an extended position to a retracted position when a ledge is disengage from a catch by a ramped surface of a female housing and a retraction tab of the female housing is configured to move the male blade terminal protector from the retracted position to the extended position as the female connector is disengaged from the male connector.

Abstract: An electrical connector can include a male blade terminal protector that protects one or more male blade terminals from external objects before, during, and after coupling of the male connector to a female connector. The male blade terminal protector can be slidably disposed within a housing of the male connector and configured to retract when the female connector is coupled to the male connector and extend when the female connector is decoupled from the male connector. The male blade terminal protector is moveable from an extended position to a retracted position when a ledge is disengage from a catch by a ramped surface of a female housing and a retraction tab of the female housing is configured to move the male blade terminal protector from the retracted position to the extended position as the female connector is disengaged from the male connector.

Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.

Abstract: Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.

Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.

Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Abstract: A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required.

Abstract: A method of forming a contact in a semiconductor device provides a titanium contact layer in a contact hole and a MOCVD-TiN barrier metal layer on the titanium contact layer. Impurities are removed from the MOCVD-TiN barrier metal layer by a plasma treatment in a nitrogen-hydrogen plasma. The time period for plasma treating the titanium nitride layer is controlled so that penetration of nitrogen into the underlying titanium contact layer is substantially prevented, preserving the titanium contact layer for subsequently forming a titanium silicide at the bottom of the contact.

Abstract: The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract: A structure in a semiconductor device useful in determining an endpoint in a chemical-mechanical polishing process is provided. The structure comprises a dielectric layer, an anti-reflective coating, and a metal layer. The dielectric layer has an opening extending therein. The anti-reflective coating extends over at least a portion of the first dielectric layer. The metal layer extends over at least a portion of the anti-reflective coating and within the opening. Thus, during the CMP process, the metal layer is removed, exposing the anti-reflective coating but leaving the metal layer in the opening to form a metal interconnect.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

Abstract: Integration schemes are presented which provide for decoupling the placement of deep source/drain (S/D) implants with respect to a selective epitaxial growth (SEG) raised S/D region, as well as decoupling silicide placement relative to a raised S/D feature. These integration schemes may be combined in multiple ways to permit independent control of the placement of these features for optimizing device performance. The methodology utilizes multiple spacers to decrease current crowding effects in devices due to proximity effects between LDD and deep S/D regions in reduced architecture devices.

Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.