Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.

Abstract: A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: A method of forming a contact in a semiconductor device deposits a refractory metal contact layer in a contact hole on a conductive region portion in a silicon substrate. The refractory metal contact layer is reacted with the silicide region prior to a plasma treatment of a contact barrier metal layer formed within the contact hole. This prevents portions of the refractory metal contact layer from being nitridated prior to conversion to silicide.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

Abstract: An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Abstract: A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.

Abstract: A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

Abstract: A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.

Abstract: A method to improve LDD corner control during a local interconnect trench oxide etch on a semiconductor device by providing a first etch stop layer over the gate and active regions in the substrate and further providing thereon a second etch stop layer made of polysilicon and having of a different composition than that of the first etch stop layer. By forming a second etch stop layer of polysilicon the present invention improves the selectivity of the local interconnect trench oxide etch, thereby improving the ability of the first and second etch stop layers to stop the etch process at the critical interfaces.

Abstract: A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.

Abstract: Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.

Abstract: A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

Abstract: A SiON ARC/hard mask is formed on a metal layer and patterned, thereby avoiding a separate hard mask. The use of SiON as a combined ARC/hard mask enables a reduction in the height of the metal stack, thereby reducing capacitance between metal lines and increasing circuit speed. In addition, etch marginality is improved due to the reduced aspect ratio. Embodiments include forming a thin silicon oxide layer on the SiON arc/hard mask before depositing a deep UV photoresist layer to minimize footing.

Abstract: A method of performing ultra-shallow junctions in a semiconductor wafer uses a silicon layer to achieve ultra-low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of the semiconductor device. After a rapid thermal annealing is performed to form the high-ohmic phase of the salicide, a silicon layer is deposited at a low temperature over the semiconductor device. The silicon layer provides a source of silicon for consumption during a second thermal annealing step, reducing the amount of silicon of the source/drain junctions that is consumed. The second thermal annealing step is performed in a nitrogen and oxygen atmosphere so at the silicon layer is transformed into a silicon oxynitride bottom anti-reflective coating layer.

Abstract: A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

Abstract: A method and arrangement for forming a local interconnect without etching completely through a junction and causing device shorts introduces an additional ion implantation step following the etching of the local interconnect opening into the substrate. The additional ion implantation step into the active region ensures that the depth of the junction is below the depth reached by the local interconnect opening and the substrate.

Abstract: A method for reducing stress in a TiN layer of a metallization structure, and a silicon wafer portion made by this method. The surface of the dielectric under the TiN is roughened using a water polish with a hard pad, to provide micromounts and valleys on the dielectric surface.